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| 型號(hào)： | AD7679CB1 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC |
| 中文描述： | 18位，2.5 LSB INL和570 kSPS的SAR型ADC |
| 文件頁(yè)數(shù)： | 20/28頁(yè) |
| 文件大小： | 506K |
| 代理商： | AD7679CB1 |
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AD7679
DIGITAL INTERFACE
The AD7679 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7679 digital interface also accommodates both 3 V and 5 V
logic by simply connecting the AD7679’s OVDD supply pin to
the host system interface digital supply. Finally, by using the
OB/2C input pin in any mode but 18-bit interface mode, both
twos complement and straight binary coding can be used.
Rev. 0 | Page 20 of 28
The two signals, CS and RD, control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7679 in
multicircuit applications, and is held low in a single AD7679
design. RD is generally used to enable the conversion result on
the data bus.
t
9
RESET
DATA
BUS
BUSY
CNVST
t
8
03085-0-035
Figure 33. RESET Timing
CNVST
BUSY
DATA
BUS
CS = RD = 0
PREVIOUS CONVERSION DATA
NEW DATA
t
1
t
10
t
4
t
3
t
11
03085-0-036
Figure 34. Master Parallel Data Timing for Reading (Continuous Read)
PARALLEL INTERFACE
The AD7679 is configured to use the parallel interface with an
18-bit, a 16-bit, or an 8-bit bus width, according to Table 7. The
data can be read either after each conversion, which is during
the next acquisition phase, or during the following conversion,
as shown in Figure 35 and Figure 36, respectively. When the
data is read during the conversion, however, it is recommended
that it is read only during the first half of the conversion phase.
This avoids any potential feedthrough between voltage
transients on the digital interface and the most critical analog
conversion circuitry. Refer to Table 7 for a detailed description
of the different options available.
DATA
BUS
t
12
t
13
BUSY
CS
RD
CURRENT
CONVERSION
03085-0-037
Figure 35. Slave Parallel Data Timing for Reading (Read after Convert)
CS = 0
CNVST,
RD
t
1
PREVIOUS
CONVERSION
DATA
BUS
t
12
t
13
BUSY
t
4
t
3
03085-0-038
Figure 36. Slave Parallel Data Timing for Reading (Read during Convert)
CS
RD
A0, A1
PINS D[15:8]
PINS D[7:0]
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
LOW BYTE
HIGH BYTE
HI-Z
HI-Z
t
12
t
12
t
13
03085-0-039
Figure 37. 8-Bit and 16-Bit Parallel Interface
SERIAL INTERFACE
The AD7679 is configured to use the serial interface when
MODE0 and MODE1 are held high. The AD7679 outputs 18
bits of data, MSB first, on the SDOUT pin. This data is
synchronized with the 18 clock pulses provided on the SCLK
pin. The output data is valid on both the rising and falling edge
of the data clock.
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