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參數資料
型號: AD7679CB1
廠商: Analog Devices, Inc.
英文描述: 18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC
中文描述: 18位,2.5 LSB INL和570 kSPS的SAR型ADC
文件頁數: 21/28頁
文件大小: 506K
代理商: AD7679CB1
AD7679
MASTER SERIAL INTERFACE
Internal Clock
The AD7679 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7679 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. Figure 38 and Figure 39 show
the detailed timing diagrams of these two modes.
In Read during Conversion mode, the serial clock and data
toggle at appropriate instants, minimizing potential feedthrough
between digital activity and critical conversion decisions.
In Read after Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns low after the 18 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
Usually, because the AD7679 is used with a fast throughput, the
mode master read during conversion is the most recommended
serial mode.
t
3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
1
2
3
16
17
18
D17
D16
D2
D1
D0
X
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t
14
t
20
t
15
t
16
t
22
t
23
t
29
t
28
t
18
t
19
t
21
t
30
t
25
t
24
t
26
t
27
03085-0-040
Figure 38. Master Serial Data Timing for Reading (Read after Convert)
Rev. 0 | Page 21 of 28
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