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參數(shù)資料
| 型號： | AD7721SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL/PARALLEL ACCESS, CDIP28 |
| 封裝： | CERDIP-28 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 259K |
| 代理商： | AD7721SQ |
AD7721
REV. A
–10–
Standby
T he part can be put into a low power standby mode by writing
to the configuration register in parallel mode or by taking the
ST BY pin high in serial mode. During Standby, the clock to
both the modulator and the digital filter is turned off and bias is
removed from all analog circuits. On coming out of standby
mode, the
DRDY
pin remains high in parallel mode and low in
serial mode for 2080 clock cycles. When
DRDY
changes state,
valid data is available at the interface. As soon as the part is
taken out of standby mode, a synchronization or calibration
cycle can be initiated.
DVAL
T he DVAL pin or the DVAL/
SYNC
pin, when programmed as
a DVAL pin, is used to indicate that an overrange input signal
has resulted in invalid data at the ADC output. Small overloads
will result in DVAL going low and the output being clipped to
positive or negative full scale, depending on the sign of the
overload. As with all single bit DAC high order sigma-delta
modulators, large overloads on the inputs can cause the modula-
tor to go unstable. T he modulator is designed to be stable with
signals within the input bandwidth that exceed full scale by
20%. When instability is detected by internal circuits, the
modulator is reset to a stable state and DVAL is held low for
2080 clock cycles. During this period, the output registers are
set to negative full scale. Whenever DVAL goes low,
DRDY
will
continue to indicate that there is data to be read.
Varying the Master Clock Frequency
T he AD7721 can be operated with clock frequencies less than
10 MHz. T he sample rate, output word rate and cutoff fre-
quency of the FIR filters are directly proportional to the master
clock frequency. T he analog input is sampled at a frequency of
2 f
CLK
while the output word rate equals f
CLK
/32. For example,
reducing the clock frequency to 5 MHz leads to a sample fre-
quency of 10 MHz, an output word rate of 156.25kHz and a
corner frequency of 76.4 kHz. T he AD7721 can be operated
with clock frequencies down to 100 kHz.
Power Supply Sequencing
If separate analog and digital supplies are used, care must be
taken to ensure that both supplies remain within
±
0.3 V of each
other both during normal operation and during power-up and
power-down to completely eliminate the possibility of latch-up.
If this cannot be assured, then the protection circuit shown in
Figure 7 is recommended. T he 10
resistors may be required to
limit the current through the diodes if particularly fast edges are
expected on the supplies during power-up and power-down.
If only one supply is available, then DV
DD
must be connected to
the analog supply. Supply decoupling capacitors are still re-
quired as close as possible to both supply pins.
10nF
1
m
F
10nF
1
m
F
10
V
10
V
IN4148
IN4148
AV
DD
DV
DD
AD7721
Figure 7. Powering-Up Protection Scheme
switching the positive input of the modulator to the reference
voltage and the negative input to AGND. Again, when the
modulator and digital filter settle, a gain correction factor is
calculated from the average of 8 output results and stored in the
gain register. After the calibration registers have been loaded
with new values, the inputs of the modulator are switched back
to the input pins. However, correct data is available at the inter-
face only after the modulator and filter have settled to the new
input values.
T he whole calibration cycle is controlled by internal logic, and the
controller need only initiate the cycle. T he calibration values
loaded into the registers only apply for the particular analog input
mode (bipolar/unipolar) selected when initiating the calibration
cycle. On changing to a different analog input mode, a new calibra-
tion must be performed. T he duration of the calibration cycle is up
to 6720 clock cycles for the unipolar mode and up to 9024 clock
cycles for the bipolar mode. Until valid data is available at the
interface, the
DRDY
pin remains high in parallel mode and low in
serial mode. Should the part see a rising edge on the
SYNC
pin in
serial mode or on the DVAL /
SYNC
pin (if programmed as a
SYNC
pin), then the calibration cycle is discontinued and a syn-
chronization operation will be performed. Similarly, putting the
part into standby mode during the cycle will discontinue the cali-
bration cycle.
T he calibration registers are static and retain their contents even
during standby. T hey need to be updated only if unacceptable
drifts in analog offsets or gain are expected. On power-up in
parallel mode, the offset and gain errors may contain incorrect
values and therefore a calibration must be performed at least
once after power-up. In serial mode, a calibration on power-up
is not mandatory if the CAL pin is grounded prior to power-up
as the calibration register will be reset to zero. Before initiating a
calibration routine, ensure that the supplies have settled and that
the voltage on the analog input pins is between the supply voltages.
Calibration does not affect the synchronization of the part.
Synchronization
Data is presented at the interface at 1/32 the CLK frequency. In
order that this data is presented to the interface at a known
point in time or to ensure that the data from more than one
device is a filtered and decimated result derived from the same
input samples, a synchronizing function has been provided. In
parallel mode, the DVAL/
SYNC
pin must first be configured as
a
SYNC
pin by writing to the control register. In serial mode,
there is a dedicated
SYNC
pin. On the rising edge of the
SYNC
pulse or the DVAL/
SYNC
pulse, the digital filter is reset to a
known state. For 2080 clock cycles,
DRDY
remains high in
parallel mode and low in serial mode. When
DRDY
changes
state at the end of this period, valid data is available at the inter-
face. Synchronizing the part has no affect on the values in the
calibration register.
SYNC
is latched internally on the rising edge of DCLK which is
a delayed version of the clock on the CLK pin. Should
SYNC
go high coincidentally with DCLK , there is a potential uncer-
tainty of one clock cycle in the start of the synchronization cycle.
T o avoid this,
SYNC
should be taken high after the falling edge
of the clock on the CLK pin and before the rising edge of this
clock.
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