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參數資料
| 型號： | AD7721SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL/PARALLEL ACCESS, CDIP28 |
| 封裝： | CERDIP-28 |
| 文件頁數： | 7/16頁 |
| 文件大小： | 259K |
| 代理商： | AD7721SQ |
AD7721
REV. A
–7–
Parallel Mode Only
Mnemonic
Function
CS
RD
WR
DRDY
Chip Select Logic Input.
Read Logic Input. T his digital input is used in conjunction with
CS
to read data from the device.
Write Logic Input. T his digital input is used in conjunction with
CS
to write data to the control register.
In parallel interface mode, a falling edge on
DRDY
indicates that new data is available to be read from the
interface. During a synchronization or calibration cycle,
DRDY
remains high until valid data is available.
T he function of this pin is determined by the state of bit DB3 in the control register. Writing a logic zero to
bit DB3 will program this pin to be a DVAL output. Writing a logic one to bit DB3 will program this pin to
be a
SYNC
input pin.
A rising edge on
SYNC
starts the synchronization cycle.
SYNC
must be pulsed low for at least one clock
cycle.
When switching this pin from
SYNC
mode to DVAL mode, it is important that there are no rising edges on
the pin which could cause resynchronization. For this purpose, an internal pull-up resistor has been included
on this pin. T hus, when the external driver driving this pin in
SYNC
mode is switched off, the DVAL/
SYNC
pin remains high.
T hese pins are both data outputs and control register inputs. Output data is placed on these pins by taking
RD
and
CS
low. Data on these pins is read into the control register by toggling
WR
low with
CS
low. With
RD
high, these pins are high impedance.
DVAL/
SYNC
SDAT A/DB11–
ST BY/DB0
Control functions such as CAL,
UNI
and ST BY, which are available as pins in serial mode, are available as bits in parallel mode.
T able I lists the contents of the control register onboard the AD7721. T his register is written to in parallel mode using the
WR
pin.
T able I. Function of Control Register Bits
Control
Register
Bit
Logical
State
Function
Mode
DB0
ST BY
0
1
0
1
Normal Operation.
Power-Down (Standby) Mode.
Normal Operation.
Writing a Logic “1” to this bit starts a calibration cycle. Internal logic resets this bit to zero at the end of
calibration.
Unipolar Mode.
Bipolar Mode.
Sets DVAL/
SYNC
Pin to DVAL Mode.
Sets DVAL/
SYNC
Pin to
SYNC
Mode.
T his bit is used for testing the AD7721. A logic low MUST be written into this bit for normal
operation.
DB1
CAL
DB2
UNI
0
1
0
1
0
DB3
DVAL/
SYNC
DB9
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