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參數(shù)資料
| 型號(hào)： | AD7721SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL/PARALLEL ACCESS, CDIP28 |
| 封裝： | CERDIP-28 |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大小： | 259K |
| 代理商： | AD7721SQ |
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AD7721
REV. A
–6–
PIN FUNCT ION DE SCRIPT IONS
Mnemonic
Function
AV
DD
AGND
DV
DD
DGND
DSUBST
Analog Positive Supply Voltage, +5 V
±
5%.
Ground reference point for analog circuitry.
Digital Supply Voltage, +5 V
±
5%.
Ground reference point for digital circuitry. DGND must be connected via its own short path to AGND (Pin 24).
T his is the substrate connection for digital circuits. It must be connected via its own short path to AGND
(Pin 24).
Analog Input. In unipolar operation, the analog input range on VIN1 is VIN2 to (VIN2 + V
REFIN
); for bipolar
operation, the analog input range on VIN1 is (VIN2
±
V
REFIN
/2). T he absolute analog input range must lie
between 0 and AV
DD
. T he analog input is continuously sampled and processed by the analog modulator.
Reference Input. T he AD7721 operates with an external reference, of value 2.5 V nominal. A suitable refer-
ence for operation with the AD7721 is the AD780. A 100 nF decoupling capacitor is required between
REFIN and AGND.
CMOS Logic Clock Input. T he AD7721 operates with an external clock which is connected to the CLK pin.
T he modulator samples the analog input on both phases of the clock, increasing the sampling rate to 20 MHz
(CLK = 10 MHz) or 30 MHz (CLK = 15 MHz).
VIN1
VIN2
REFIN
CLK
Serial Mode Only
CS
,
RD
,
WR
T o select the serial interface mode of operation, the AD7721 must be powered up with
CS
,
RD
and
WR
all
tied to DGND. After two clock cycles, the AD7721 switches into serial mode. T hese pins must remain low
during serial operation.
In the serial interface mode, a rising edge on
DRDY
indicates that new data is available to be read from the
interface. During a synchronization or calibration cycle,
DRDY
remains low until valid data is available.
Serial Data Output. Output serial data becomes active after
RFS
goes low. Sixteen bits of data are clocked
out starting with the MSB. Serial data is clocked out on the rising edge of SCLK and is valid on the subse-
quent falling edge of SCLK .
Receive Frame Synchronization. Active low logic input. T his is a logic input with
RFS
provided by connect-
ing this input to
DRDY
. When
RFS
is high, SDAT A is high impedance.
T his is a test mode pin. T his pin must be tied to DGND.
T his is a test mode pin. T his pin must be tied to DGND.
Serial Clock. Logic Output. T he internal digital clock is provided as an output on this pin. Data is output
from the AD7721 on the rising edge of SCLK and is valid on the falling edge of SCLK .
T his is a test mode pin. T his pin must be tied to DGND.
Synchronization Logic Input. A rising edge on
SYNC
starts the synchronization cycle.
SYNC
must be
pulsed low for at least one clock cycle to initiate a synchronization cycle.
T his is a test mode pin. T his pin must be tied to DGND.
T his is a test mode pin. T his pin must be tied to DGND.
Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A logic high selects
bipolar mode.
Calibration Mode Logic Input. CAL must go high for at least one clock cycle to initiate a calibration cycle.
Standby Mode Logic Input. A logic high on this pin selects standby mode.
Data Valid Digital Output. In serial mode, this pin is a dedicated data valid pin.
DRDY
SDAT A/DB11
RFS
/DB10
DB9
DB8
SCLK /DB7
DB6
SYNC
/DB5
DB4
DB3
UNI
/DB2
CAL/DB1
ST BY/DB0
DVAL/
SYNC
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