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參數(shù)資料
| 型號： | AD7721SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL/PARALLEL ACCESS, CDIP28 |
| 封裝： | CERDIP-28 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 259K |
| 代理商： | AD7721SQ |
AD7721
TIMNGCHARACTERISTICS
1, 2
REV. A
–4–
Limit at T
MIN
, T
MAX
(A, S Versions)
Parameter
Units
Conditions/Comments
Serial Interface
f
CLK3
100
15
0.45
×
t
CLK
0.45
×
t
CLK
t
CLK
t
CLK HI
– 10
20
t
CLK HI
t
CLK LO
25
0
0
20
32
×
t
CLK
kHz min
MHz max
ns min
ns min
ns nom
ns min
ns max
ns nom
ns nom
ns max
ns min
ns min
ns max
ns nom
Master Clock Frequency
15 MHz for Specified Performance
Master Clock Input Low T ime
Master Clock Input High T ime
DRDY
High T ime
RFS
Low to SCLK Falling Edge Setup T ime
RFS
Low to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Rising Edge to Data Valid Delay
RFS
to SCLK Falling Edge Hold T ime
Bus Relinquish T ime after Rising Edge of
RFS
t
CLK LO
t
CLK HI
t
1
t
24
t
3
t
4
t
5
t
6
t
7
t
85
t
9
Parallel Interface
f
CLK3
Period between Consecutive
DRDY
Rising Edges
100
10
0.45
×
t
CLK
0.45
×
t
CLK
kHz min
MHz max
ns min
ns min
Master Clock Frequency
10 MHz for Specified Performance
Master Clock Input Low T ime
Master Clock Input High T ime
t
CLK LO
t
CLK HI
Read Operation
t
10
t
11
t
12
Write Operation
t
13
t
14
t
15
2
×
t
CLK
30
32
×
t
CLK
ns nom
ns max
ns nom
DRDY
High T ime
Data Access T ime after Falling Edge of
DRDY
Period between Consecutive
DRDY
Rising Edges
35
20
0
ns min
ns min
ns min
WR
Pulse Width
Data Valid to
WR
High Setup T ime
Data Valid to
WR
High Hold T ime
NOT ES
T he timing is measured with a load of 50 pF on SCLK and
DRDY
. SCLK can be operated with a load capacitance of 50 pF maximum.
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
All digital outputs are timed with the load circuit below and, except for t
2
, are defined as the time required for an output to cross 0.8 V or 2 V, whichever occurs last.
3
T he AD7721 is production tested with f
CLK
at 10 MHz for parallel mode operation and at 15 MHz for serial mode operation. However, it is guaranteed by character-
ization to operate with CLK frequencies down to 100 kHz.
4
t
2
is the time from
RFS
crossing 1.6 V to SCLK crossing 0.8 V.
5
t
8
and t
15
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown below. T he measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. T his means that the time quoted in the T iming Characteristics is the true bus
relinquish time of the part and, as such, is independent of external bus loading capacitance.
TO
OUTPUT
PIN
+1.6V
I
OH
I
OL
C
L
50pF
1.6mA
200
m
A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
(AV
DD
= +5 V
6
5%; DV
DD
= +5 V
6
5%; AGND = DGND = 0 V, REFIN= +2.5 V
unless otherwse noted)
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