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參數資料
| 型號： | AD7722 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 195 kSPS CMOS, Sigma-Delta ADC |
| 中文描述： | 16位，195 kSPS的的CMOS，Σ-Δ模數轉換器 |
| 文件頁數： | 13/24頁 |
| 文件大小： | 526K |
| 代理商： | AD7722 |
AD7722
–13–
REV. 0
CIRCUIT DESCRIPTION
The AD7722 ADC employs a sigma-delta conversion technique
that converts the analog input into a digital pulse train. The
analog input is continuously sampled by a switched capacitor
modulator at twice the rate of the clock input frequency, 2
×
f
CLKIN
. The digital data that represents the analog input is in
the 1’s density of the bit stream at the output of the sigma-delta
modulator. The modulator outputs a bit stream at a data rate
equal to f
CLKIN
.
Due to the high oversampling rate, which spreads the quantiza-
tion noise from 0 to f
CLKIN
/2, the noise energy contained in the
band of interest is reduced (Figure 24a). To reduce the quanti-
zation noise further, a high order modulator is employed to
shape the noise spectrum so that most of the noise energy is
shifted out of the band of interest (Figure 24b).
The digital filter that follows the modulator provides three main
functions. The filter performs sophisticated averaging on the
1 bit samples from the output of the modulator, while removing
the large out of band quantization noise (Figure 24c). Lastly the
digital filter reduces the data rate from f
CLKIN
at the input of the
filter to f
CLKIN
/64 at the output of the filter. The AD7722
output data rate, F
S
, is a little over twice the signal bandwidth,
which guarantees that there is no loss of data in the signal band.
Digital filtering has certain advantages over analog filtering.
First, since digital filtering occurs after the A/D conversion, it
can remove noise injected during the conversion process.
Analog filtering cannot remove noise injected during conver-
sion. Second, the digital filter combines low pass-band ripple
with a steep roll off, while also maintaining a linear phase
response.
BAND OF INTEREST
f
CLKIN
/2
DIGITAL FILTER CUTOFF FREQUENCY
WHICH EQUALS 97.65kHz (12.5MHz)
BAND OF INTEREST
QUANTIZATION NOISE
f
CLKIN
/2
BAND OF INTEREST
f
CLKIN
/2
NOISE SHAPING
a.
b.
c.
Figure 24. Sigma-Delta ADC
The AD7722 employs two Finite Impulse Response (FIR) filters
in series. The first filter is a 384 tap filter that samples the output
of the modulator at f
CLKIN
. The second filter is a 151 tap half-
band filter that samples the output of the first filter at f
CLKIN
/32
and decimates by 2. The implementation of this filter architec-
ture results in a filter with a group delay of 42 conversions (84
conversions for settling to a full-scale step).
The digital filter provides 6 dB of attenuation at a frequency
(f
CLKIN
/128) one-half its output rate. With a clock frequency
of 12.5 MHz, the digital filter has a pass-band frequency of
90.625 kHz, a cutoff frequency is 96.92 kHz and stop-band
frequency of 104.6875 kHz.
Due to the sampling nature of the digital filter, the filter does
not provide any rejection at integer multiples of its input
sampling frequency. The filter response in Figure 25a shows the
unattenuated frequency bands occurring at n
×
f
CLKIN
where
n = 1, 2, 3. . . . At these frequencies, there are frequency bands
±
f
3 dB
wide (f
3 dB
is the –3 dB bandwidth of the digital filter) on
either side of n
f
CLKIN
where noise passes unattenuated to the
output. Out of band signals coincident with any of the filter
images are aliased into the pass band. However, due to the
AD7722’s high oversampling ratio, these bands occupy only a
small fraction of the spectrum, and most broadband noise is
filtered. This means that the antialias filtering requirements in
front of the AD7722 are considerably reduced versus a conven-
tional converter with no on-chip filtering. Figure 25b shows the
frequency response of an antialias filter. With a –3 dB corner
frequency set at f
CLKIN
/64, a single pole filter will provide 36 dB
of attenuation at f
CLKIN
.
Depending on the application, however, it may be necessary to
provide additional antialias filtering prior to the AD7722 to
eliminate unwanted signals from the frequency bands the digital
filter passes. It may also be necessary in some applications to
provide analog filtering in front of the AD7722 to ensure that
differential noise signals outside the band of interest do not
saturate the analog modulator.
1f
CLKIN
0dB
2f
CLKIN
3f
CLKIN
Figure 25a. Digital Filter Frequency Response
OUTPUT
DATA RATE
f
CLKIN
/64
0dB
f
CLKIN
ANTIALIAS FILTER
RESPONSE
REQUIRED
ATTENUATION
Figure 25b. Frequency Response of Antialias Filter
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PDF描述 |
|---|---|
| AD7722AS | 16-Bit, 195 kSPS CMOS, Sigma-Delta ADC |
| AD7723 | 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| AD7723BS | 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| AD7724AST | Dual CMOS Modulators |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7722AS | 制造商:Rochester Electronics LLC 功能描述:16-BIT SIGMA-DELTA CONVERTER I.C. - Bulk 制造商:Analog Devices 功能描述:A/D Converter (A-D) IC |
| AD7722AS-ES | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD7722ASZ | 功能描述:IC ADC 16BIT 195KSPS 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD7722CSZ | 制造商:Analog Devices 功能描述: |
| AD7723 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
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