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參數(shù)資料
| 型號： | AD7722 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 195 kSPS CMOS, Sigma-Delta ADC |
| 中文描述： | 16位，195 kSPS的的CMOS，Σ-Δ模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大小： | 526K |
| 代理商： | AD7722 |
AD7722
–18–
REV. 0
Offset and Gain Calibration
A calibration of offset and gain errors can be performed in both
serial and parallel modes by initiating a calibration cycle. During
this cycle, offset and gain registers in the filter are loaded with
values representing the dc offset of the analog modulator and a
modulator gain correction factor. The correction factors are
determined by an on-chip microcontroller measuring the
conversion results for three different input conditions: minus
full scale (–FS), plus full scale (+FS), and midscale. In normal
operation, the offset register is subtracted from the digital filter
output, and this result is then multiplied by the gain correction
factor to obtain an offset and gain corrected final result.
The calibration cycle is controlled by internal logic, and the user
need only initiate the cycle. A calibration is initiated when the
rising edge of CLKIN senses a high level on the CAL input.
There is an uncertainty of up to 64 CLKIN cycles before the
calibration cycle actually begins because the current conversion
must complete before calibration commences. The calibration
values loaded into the registers only apply for the particular
analog input mode (bipolar/unipolar) selected when initiating
the calibration cycle. On changing to a different analog input
mode, a new calibration must be performed.
During the calibration cycle, in unipolar mode, the offset of the
analog modulator is evaluated; the differential inputs to the
modulator are shorted internally to AGND. Once calibration
begins, DVAL goes low and
DRDY
goes high indicating there is
invalid data in the output register. After 8192 CLKIN cycles,
when the modulator and digital filter settle, the average of eight
output results (512 CLKIN cycles) is calculated and stored in
the offset register. In unipolar mode, this result also represents
minus full scale, required to calculate the gain correction factor.
The gain correction factor can then be determined by internally
switching the inputs to +FS (V
REF2
). The positive input of the
modulator is switched to the reference voltage and the negative
input to AGND. Again, when the modulator and digital filter
settle, the average of the eight output results is used to calculate
the gain correction factor.
In bipolar mode, an additional measurement is required since
zero scale is not the same as –FS. Therefore, calibration in
bipolar mode requires an additional 8704 CLKIN cycles. Zero
scale is similarly determined by shorting both analog inputs to
AGND. Then the inputs are internally reconfigured to apply
+FS and –FS (+V
REF2
/2 and –V
REF2
/2) to determine the gain
correction factor.
After the calibration registers have been loaded with new values,
the inputs of the modulator are switched back to the input pins.
However, correct data is available at the interface only after the
modulator and filter have settled to the new input values.
Should the part see a rising edge on the SYNC or RESET pin
during a calibration cycle, the calibration cycle is discontinued,
and a synchronization operation or reset will be performed.
The calibration registers are static. They need to be updated
only if unacceptable drifts in analog offsets or gain are expected.
After power-up, a RESET is not mandatory since power-on
reset circuitry clears the offset and gain registers. Care must be
taken to ensure the CAL pin is held low during power-up.
Before initiating a calibration routine, ensure the supplies and
reference input have settled, and that the voltage on the analog
input pins is between the supply voltages.
DATA INTERFACING
The AD7722 offers a choice of serial or parallel data interface
options to meet the requirements of a variety of system configu-
rations. In parallel mode, multiple AD7722s can be easily
configured to share a common data bus. Serial mode is ideal
when it is required to minimize the number of data interface
lines connected to a host processor. In either case, careful
attention to the system configuration is required to realize the
high dynamic range available with the AD7722. Consult the
recommendations in the “Power Supply Grounding and
Layout” section. The following recommendations for parallel
interfacing also apply for the system design in serial mode.
Parallel Interface
When using the AD7722, place a buffer/latch adjacent to the
converter to isolate the converter’s data lines from any noise
which may be on the data bus. Even though the AD7722 has
three-state outputs, use of an isolation latch represents good
design practice. This arrangement will inject a small amount of
digital noise on the AD7722 ground plane; these currents
should be quite small and can be minimized by ensuring that
the converter input/output does not drive a large fanout (they
normally can’t by design). Minimizing the fanout on the
AD7722’s digital port will also keep the converter logic transi-
tions relatively free from ringing and thereby minimize any
potential coupling into the analog port of the converter.
The simplified diagram (Figure 38) shows how the parallel
interface of the AD7722 can be configured to interface with the
system data bus of a microprocessor or a modern microcontrol-
ler such as the MC68HC16 or 8XC251.
AD7722
ADDR
DECODE
DB0–15
DRDY
CS
RD
16
16
74XX16374
OR
74XX16244
OE
D0–15
RD
INTERRUPT
ADDR
DSP/μC
Figure 38. Parallel Interface Connection
With
CS
and
RD
tied permanently low the data output bits are
always active. When the
DRDY
output goes high for two
CLKIN cycles, the rising edge of
DRDY
is used to latch the
conversion data before a new conversion result is loaded into the
output data register. The falling edge of
DRDY
then sends an
appropriate interrupt signal for interface control. Alternatively
if buffers are used instead of latches the falling edge of
DRDY
provides the necessary interrupt when a new output word is
available from the AD7722.
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PDF描述 |
|---|---|
| AD7722AS | 16-Bit, 195 kSPS CMOS, Sigma-Delta ADC |
| AD7723 | 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| AD7723BS | 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| AD7724AST | Dual CMOS Modulators |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7722AS | 制造商:Rochester Electronics LLC 功能描述:16-BIT SIGMA-DELTA CONVERTER I.C. - Bulk 制造商:Analog Devices 功能描述:A/D Converter (A-D) IC |
| AD7722AS-ES | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD7722ASZ | 功能描述:IC ADC 16BIT 195KSPS 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7722CSZ | 制造商:Analog Devices 功能描述: |
| AD7723 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
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