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參數資料
| 型號： | AD7730LBRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數： | 28/52頁 |
| 文件大?。?/td> | 497K |
| 代理商： | AD7730LBRU |
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AD7730/AD7730L
–28–
REV. A
Because of this effect, care should be taken in choosing an out-
put rate that is close to the line frequency in the application. If
the line frequency is 50 Hz, an output update rate of 50 Hz
should not be chosen as it will significantly reduce the AD7730’s
line frequency rejection (the 50 Hz will appear as a dc effect
with only 6 dB attenuation). Choosing an output rate of 55 Hz
will result in a 6 dB—attenuated aliased frequency of 5 Hz with
only a further 25 dB attenuation based on the filter profile. T his
number is based on the filter roll-off and Figure 11 can be used
as a reference by dividing the frequency scale by a factor of 4.
Choosing 57 Hz as the output rate will give better than 90 dB
attenuation of the aliased line frequency which appears as a
7 Hz signal. Similarly, multiples of the line frequency should be
avoided as the output rate because harmonics of the line fre-
quency will not be fully attenuated. T he programmability of the
AD7730’s output rate should allow the user to readily choose an
output rate that overcomes this issue. An alternative is to use
the part in nonchop mode.
Figure 13 shows the frequency response for the AD7730 with
the second stage filter set for normal FIR operation, chop mode
disabled, the decimal equivalent of the word in the SF bits set to
1536 and a master clock frequency of 4.9152 MHz. T he response
is analogous to that of Figure 11, with the three-times-larger SF
word producing the same 200 Hz output rate. Once again, the
response will scale proportionally with master clock frequency.
T he response is shown from dc to 100 Hz. T he rejection at
50 Hz
±
1 Hz, and 60 Hz
±
1 Hz is better than 88 dB.
FREQUENCY – Hz
0
–60
–100
0
90
G
10
20
30
40
50
60
70
80
–10
–50
–70
–90
–30
–40
–80
–20
–120
–110
100
Figure 13. Detailed Full Frequency Response of AD7730
(Second Stage Filter as Normal FIR, Chop Disabled)
T he –3 dB frequency for the frequency response of the AD7730
with the second stage filter set for normal FIR operation and
chop mode enabled, is determined by the following relationship:
f
3
dB
=
0.039
×
f
CLK IN
16
×
1
SF
In this case,
f
3 dB
=
7.8 Hz
and the stop band, where the attentua-
tion is greater than 64.5 dB, is determined by:
f
STOP
=
0.14
×
f
CLK IN
16
×
1
SF
In this case,
f
3 dB
=
28 Hz.
Figure 14 shows the frequency response for the same set of
conditions as for Figure 13, but in this case the response is
shown out to 600 Hz. T his plot is comparable to that of Figure
12. T he most notable difference is the absence of the peaks in
the response at 200 Hz and 400 Hz. As a result, interference at
these frequencies will be effectively eliminated before being
aliased back to dc.
FREQUENCY – Hz
0
–60
–100
0
450
G
50
100 150 200 250 300 350 400
–10
–50
–70
–90
–30
–40
–80
–20
–120
–110
500 550
600
Figure 14. Expanded Full Frequency Response of AD7730
(Second Stage Filter as Normal FIR, Chop Disabled)
相關PDF資料 |
PDF描述 |
|---|---|
| AD7730 | Bridge Transducer ADC |
| AD7730BN | Bridge Transducer ADC |
| AD7730BR | Bridge Transducer ADC |
| AD7730BRU | Bridge Transducer ADC |
| AD7730L | Bridge Transducer ADC |
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| AD7730LBRUZ-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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