- 您現在的位置：買賣IC網 > PDF目錄373915 > AD7730LBRU (ANALOG DEVICES INC) Bridge Transducer ADC PDF資料下載
參數資料
| 型號： | AD7730LBRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數： | 42/52頁 |
| 文件大小： | 497K |
| 代理商： | AD7730LBRU |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當前第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
AD7730/AD7730L
–42–
REV. A
Figure 25. AD7730 with Bipolar Excitation of the Bridge
Bipolar E xcitation of the Bridge
As mentioned previously, some applications will require that the
AD7730 handle inputs from a bridge that is excited by a bipolar
voltage. T he number of applications requiring this are limited,
but with the addition of some external components the AD7730
is capable of handling such signals. Figure 25 outlines one ap-
proach to the problem.
T he example shown is a dc-excited bridge that is driven from
±
5 V supplies. In such a circuit, two issues must be addressed.
T he first is how to get the AD7730 to handle input voltages
near or below ground and the second is how to take the 10 V
excitation voltage which appears across the bridge and generate
a suitable reference voltage for the AD7730. T he circuit of Figure
25 attempts to address these two issues simultaneously.
T he AD7730’s analog and digital supplies can be split such that
AV
DD
and DV
DD
can be at separate potentials and AGND and
DGND can also be at separate potentials. T he only stipulation
is that AV
DD
or DV
DD
must not exceed the AGND by 5.5 V.
In Figure 25, the DV
DD
is operated at +3 V, which allows the
AGND to go down to –2.5 V with respect to system ground.
T his means that all logic signals to the part must not exceed 3 V
with respect to system ground. T he AV
DD
is operated at +2.5 V
with respect to system ground.
T he bridge is excited with 10 V across its inputs. T he output of
the bridge is biased around the midpoint of the excitation volt-
ages which in this case is system ground or 0 V. In order for the
common-mode voltage of the analog inputs to sit correctly, the
AGND of the AD7730 must be biased below system ground by
a minimum of 1.2 V. T he 10 V excitation voltage must be re-
duced to 5 V before being applied as the reference voltage for
the AD7730.
T he resistor string R1, R2 and R3, takes the 10 V excitation
voltage and generates differential voltage of nominally 5 V.
Amplifiers A1 and A2 buffer the resistor string voltages and
provide the AV
DD
and AGND voltages as well as the REF IN(+)
and REF IN(–) voltages for the AD7730. T he differential
reference voltage for the part is +5 V. T he AD7730 retains its
ratiometric operation with this reference voltage varying in sym-
pathy with the analog input voltage.
T he values of the resistors in the resistor string can be changed
to allow a larger DV
DD
voltage. For example, if R1 = 3 k
,
R2 = 10 k
and R3 = 7 k
, the AV
DD
and AGND voltages
become +3.5 V and –1.5 V respectively. T his allows the AD7730
to be used with a +3.6 V DV
DD
voltage while still allowing the
analog input range to be within the specified common-mode
range.
An alternate scheme to this is to generate the AV
DD
and AGND
voltages from regulators or Zener diodes driven from the +5 V
and –5 V supplies respectively. T he reference voltage for the
part would be generated in the same manner as just outlined but
amplifiers A1 and A2 would not be required to buffer the volt-
ages as they are now only driving the reference pins of the
AD7730. However, care must be taken in this scheme to ensure
that the REF IN(+) voltage does not exceed AV
DD
and that the
REF IN(–) voltage does not go below AGND.
+5V
–5V
SIGMA-
DELTA
MODULATOR
DV
DD
AD7730
6-BIT
DAC
SERIAL INTERFACE
AND CONTROL LOGIC
REGISTER BANK
CLOCK
GENERATION
PROGRAMMABLE
DIGITAL
FILTER
SIGMA-DELTA A/D CONVERTER
BUFFER
PGA
STANDBY
SYNC
MCLK IN
MCLK OUT
SCLK
CS
DIN
DOUT
RESET
RDY
POL
DGND
MUX
CALIBRATION
MICROCONTROLLER
+
IN+
OUT–
IN–
OUT+
REF IN(+)
AV
DD
AIN1(+)
AIN1(–)
SYSTEM
GROUND
+3V
A1
A2
+5V
–5V
+5V
–5V
R1
5k
R2
10k
R3
5k
1/2 OP284
OR 1/2 OP213
1/2 OP284
OR 1/2 OP213
REF IN(–)
AGND
ALL VOLTAGE VALUES ARE WITH
RESPECT TO SYSTEM GROUND.
+/–
相關PDF資料 |
PDF描述 |
|---|---|
| AD7730 | Bridge Transducer ADC |
| AD7730BN | Bridge Transducer ADC |
| AD7730BR | Bridge Transducer ADC |
| AD7730BRU | Bridge Transducer ADC |
| AD7730L | Bridge Transducer ADC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7730LBRU-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRUZ | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRUZ-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRUZ-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
發布緊急采購，3分鐘左右您將得到回復。