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| 型號(hào)： | AD7730LBRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁(yè)數(shù)： | 29/52頁(yè) |
| 文件大小： | 497K |
| 代理商： | AD7730LBRU |
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AD7730/AD7730L
REV. A
–29–
FAST Step Mode
T he second mode of operation of the second stage filter is in
FAST
Step
mode which enables it to respond rapidly to step
inputs. T his
FAST
Step
mode is enabled by placing a 1 in the
FAST bit of the Filter Register. If the FAST bit is 0, the part
continues to process step inputs with the normal FIR filter as
the second stage filter. With
FAST
Step
mode enabled, the
second stage filter will continue to process steady state inputs
with the filter in its normal FIR mode of operation. However,
the part is continuously monitoring the output of the first stage
filter and comparing it with the second previous output. If the
difference between these two outputs is greater than a predeter-
mined threshold (1% of full scale), the second stage filter switches
to a simple moving average computation. When the step change
is detected, the
STDY
bit of the Status Register goes to 1 and
will not return to 0 until the FIR filter is back in the processing
loop.
T he initial number of averages in the moving average computa-
tion is either 2 (chop enabled) or 1 (chop disabled). T he num-
ber of averages will be held at this value as long as the threshold
is exceeded. Once the threshold is no longer exceeded (the step
on the analog input has settled), the number of outputs used to
compute the moving average output is increased. T he first and
second outputs from the first stage filter where the threshold is
no longer exceeded is computed as an average by two, then four
outputs with an average of four, eight outputs with an average of
eight, and six outputs with an average of 16. At this time, the
second stage filter reverts back to its normal FIR mode of opera-
tion. When the second stage filter reverts back to the normal FIR,
the
STDY
bit of the Status Register goes to 0.
Figure 15 shows the different responses to a step input with
FAST
Step
mode enabled and disabled. T he vertical axis shows
the code value returned by the AD7730 and indicates the set-
tling of the output to the input step change. T he horizontal axis
shows the number of outputs it takes for that settling to occur.
T he positive input step change occurs at the fifth output. In
FAST
Step
mode, the output has settled to the final value by the
eighth output. In normal mode, the output has not reached
close to its final value until after the 25th output.
NUMBER OF OUTPUTS
20000000
15000000
00
25
5
C
10
15
20
10000000
5000000
Figure 15. Step Response for FASTStep and Normal
Operation
In
FAST
Step
mode, the part has settled to the new value much
faster. With chopping enabled, the
FAST
Step
mode settles to
its value in two outputs, while the normal mode settling takes
23 outputs. Between the second and 23rd output, the
FAST
Step
mode produces a settled result, but with additional noise com-
pared to the specified noise level for its operating conditions. It
starts at a noise level that is comparable to SK IP mode and as
the averaging increases ends up at the specified noise level. T he
complete settling time to where the part is back within the
specified noise number is the same for
FAST
Step
mode and
normal mode. As can be seen from Figure 13, the
FAST
Step
mode gives a much earlier indication of where the output chan-
nel is going and its new value. T his feature is very useful in
weighing applications to give a much earlier indication of the
weight, or in an application scanning multiple channels where
the user does not have to wait the full settling time to see if a
channel has changed value.
SKIP Mode
T he final method for operating the second stage filter is where it
is bypassed completely. T his is achieved by placing a 1 in the
SK IP bit of the Filter Register. When SK IP mode is enabled, it
means that the only filtering on the part is the first stage, sinc
3
,
filter. As a result, the complete filter profile is as described ear-
lier for the first stage filter and illustrated in Figure 10.
In SK IP mode, because there is much less processing of the data
to derive each individual output, the normal mode settling time
for the part is shorter. As a consequence of the lesser filtering,
however, the output noise from the part will be significantly
higher for a given SF word. For example with a 20 mV, an SF
word of 1536 and CHP = 0, the output rms noise increases
from 80 nV to 200 nV. With a 10 mV input range, an SF word
of 1024 and CHP = 1, the output rms noise goes from 60 nV to
200 nV.
With chopping disabled and SK IP mode enabled, each output
from the AD7730 is a valid result in itself. However, with chop-
ping enabled and SK IP mode enabled, the outputs from the
AD7730 must be handled in pairs as each successive output is
from reverse chopping polarities.
C ALIBRAT ION
T he AD7730 provides a number of calibration options which
can be programmed via the MD2, MD1 and MD0 bits of the
Mode Register. T he different calibration options are outlined in
the Mode Register and Calibration Operations sections. A cali-
bration cycle may be initiated at any time by writing to these
bits of the Mode Register. Calibration on the AD7730 removes
offset and gain errors from the device.
T he AD7730 gives the user access to the on-chip calibration
registers allowing the microprocessor to read the device’s cali-
bration coefficients and also to write its own calibration coeffi-
cients to the part from prestored values in E
2
PROM. T his gives
the microprocessor much greater control over the AD7730’s
calibration procedure. It also means that the user can verify that
the device has performed its calibration correctly by comparing
the coefficients after calibration with prestored values in
E
2
PROM. T he values in these calibration registers are 24 bits
wide. In addition, the span and offset for the part can be adjusted
by the user.
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| AD7730 | Bridge Transducer ADC |
| AD7730BN | Bridge Transducer ADC |
| AD7730BR | Bridge Transducer ADC |
| AD7730BRU | Bridge Transducer ADC |
| AD7730L | Bridge Transducer ADC |
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| AD7730LBRU-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRUZ | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRUZ-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRUZ-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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