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參數資料
| 型號： | AD7730LBRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數： | 8/52頁 |
| 文件大小： | 497K |
| 代理商： | AD7730LBRU |
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AD7730/AD7730L
–8–
REV. A
Pin
No.
Mnemonic
Function
3
MCLK OUT
When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN
and MCLK OUT . If an external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock sig-
nal. T his clock can be used to provide a clock source for external circuits and MCLK OUT is capable of driving
one CMOS load. If the user does not require it, MCLK OUT can be turned off with the CLK DIS bit of the Mode
Register. T his ensures that the part is not burning unnecessary power driving capacitance on the MCLK OUT pin.
Clock Polarity. Logic Input. T his determines the polarity of the serial clock. If the active edge for the proces-
sor is a high-to-low SCLK transition, this input should be low. In this mode, the AD7730 puts out data on the
DAT A OUT line in a read operation on a low-to-high transition of SCLK and clocks in data from the DAT A
IN line in a write operation on a high-to-low transition of SCLK . In applications with a noncontinuous serial
clock (such as most microcontroller applications), this means that the serial clock should idle low between
data transfers. If the active edge for the processor is a low-to-high SCLK transition, this input should be high.
In this mode, the AD7730 puts out data on the DAT A OUT line in a read operation on a high-to-low transi-
tion of SCLK and clocks in data from the DAT A IN line in a write operation on a low-to-high transition of
SCLK . In applications with a noncontinuous serial clock (such as most microcontroller applications), this
means that the serial clock should idle high between data transfers.
Logic Input that allows for synchronization of the digital filters and analog modulators when using a number
of AD7730s. While
SYNC
is low, the nodes of the digital filter, the filter control logic and the calibration
control logic are reset and the analog modulator is also held in its reset state.
SYNC
does not affect the digital
interface but does reset
RDY
to a high state if it is low. While
SYNC
is asserted, the Mode Bits may be set up
for a subsequent operation which will commence when the
SYNC
pin is deasserted.
Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator and
all on-chip registers of the part to power-on status. Effectively, everything on the part except for the clock
oscillator is reset when the
RESET
pin is exercised.
Analog Output. T his analog output is an internally-generated voltage used as an internal operating bias point.
T his output is not for use external to the AD7730 and it is recommended that the user does not connect any-
thing to this pin.
Ground reference point for analog circuitry.
Analog Positive Supply Voltage. T he AV
DD
to AGND differential is 5 V nominal.
Analog Input Channel 1. Positive input of the differential, programmable-gain primary analog input pair. T he
differential analog input ranges are 0 mV to +10 mV, 0 mV to +20 mV, 0 mV to +40 mV and 0 mV to +80 mV
in unipolar mode, and
±
10 mV,
±
20 mV,
±
40 mV and
±
80 mV in bipolar mode.
Analog Input Channel 1. Negative input of the differential, programmable gain primary analog input pair.
Analog Input Channel 2 or Digital Output 1. T his pin can be used either as part of a second analog input
channel or as a digital output bit as determined by the DEN bit of the Mode Register. When selected as an
analog input, it is the positive input of the differential, programmable-gain secondary analog input pair. T he
analog input ranges are 0 mV to +10 mV, 0 mV to +20 mV, 0 mV to +40 mV and 0 mV to +80 mV in unipo-
lar mode and
±
10 mV,
±
20 mV,
±
40 mV and
±
80 mV in bipolar mode. When selected as a digital output,
this output can programmed over the serial interface using bit D1 of the Mode Register.
Analog Input Channel 2 or Digital Output 0. T his pin can be used either as part of a second analog input channel
or as a digital output bit as determined by the DEN bit of the Mode Register. When selected as an analog input, it
is the negative input of the differential, programmable-gain secondary analog input pair. When selected as a digital
output, this output can programmed over the serial interface using bit D0 of the Mode Register.
Reference Input. Positive terminal of the differential reference input to the AD7730. REF IN(+) can lie
anywhere between AV
DD
and AGND. T he nominal reference voltage (the differential voltage between REF
IN(+) and REF IN(–)) should be +5 V when the HIREF bit of the Mode Register is 1 and +2.5 V when the
HIREF bit of the Mode Register is 0.
Reference Input. Negative terminal of the differential reference input to the AD7730. T he REF IN(–) poten-
tial can lie anywhere between AV
DD
and AGND.
Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac-
excited bridge applications. When ACX is high, the bridge excitation is taken as normal and when ACX is
low, the bridge excitation is reversed (chopped). If AC = 0 (ac mode turned off) or CHP = 0 (chop mode
turned off), the ACX output remains high.
Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac-
excited bridge applications. T his output is the complement of ACX . In ac mode, this means that it toggles in
anti-phase with ACX . If AC = 0 (ac mode turned off) or CHP = 0 (chop mode turned off), the
ACX
output
remains low. When toggling, it is guaranteed to be nonoverlapping with ACX . T he non-overlap interval, when
both ACX and
ACX
are low, is one master clock cycle.
4
POL
5
SYNC
6
RESET
7
V
BIAS
8
9
AGND
AV
DD
AIN1(+)
10
11
12
AIN1(–)
AIN2(+)/D1
13
AIN2(–)/D0
14
REF IN(+)
15
REF IN(–)
16
ACX
17
ACX
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| AD7730 | Bridge Transducer ADC |
| AD7730BN | Bridge Transducer ADC |
| AD7730BR | Bridge Transducer ADC |
| AD7730BRU | Bridge Transducer ADC |
| AD7730L | Bridge Transducer ADC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7730LBRU-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRUZ | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRUZ-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRUZ-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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