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參數(shù)資料
| 型號(hào)： | AD7853LAR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 25/34頁 |
| 文件大小： | 350K |
| 代理商： | AD7853LAR |
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REV. B
–25–
AD7853/AD7853L
high after the 16th SCLK rising edge as shown by the dotted
SYNC
line in Figure 36. Thus a frame sync that gives a high
pulse, of one SCLK cycle minimum duration, at the beginning
of the read/write operation may be used. The rising edge of
SYNC
enables the three-state on the DOUT pin. The falling
edge of
SYNC
disables the three-state on the DOUT pin, and
data is clocked out on the falling edge of SCLK. Once
SYNC
goes high, the three-state on the DOUT pin is enabled. The
data input is sampled on the rising edge of SCLK and thus has
to be valid a time, t
7
, before this rising edge. The POLARITY
pin may be used to change the SCLK edge which the data is
sampled on and clocked out on. If resetting the interface is
required, the
SYNC
must be taken high and then low.
Modes 4 and 5 (Self-Clocking Modes)
The timing diagrams in Figure 38 and Figure 39 are for Inter-
face Modes 4 and 5. Interface Mode 4 has a noncontinuous
SCLK output and Interface Mode 5 has a continuous SCLK
output. These modes of operation are especially different to all
the other modes since the SCLK and
SYNC
are outputs. The
SYNC
is generated by the part as is the SCLK. The master
clock at the CLKIN pin is routed directly to the SCLK pin for
Interface Mode 5 (Continuous SCLK) and the CLKIN signal is
gated with the
SYNC
to give the SCLK (noncontinuous) for
Interface Mode 4.
Mode 2 (3-Wire SPI/QSPI Interface Mode)
This is the DEFAULT INTERFACE MODE.
In Figure 35 below we have the timing diagram for Interface
Mode 2 which is the SPI/QSPI interface mode. Here the
SYNC
input is active low and may be pulsed or tied permanently low.
If
SYNC
is permanently low 16 clock pulses must be applied to
the SCLK pin for the part to operate correctly, and with a
pulsed
SYNC
input a continuous SCLK may be applied provided
SYNC
is low for only 16 SCLK cycles. In Figure 30 the
SYNC
going low disables the three-state on the DOUT pin. The first
falling edge of the SCLK after the
SYNC
going low clocks out
the first leading zero on the DOUT pin. The DOUT pin is
three-stated again a time t
12
after the
SYNC
goes high. With the
DIN pin the data input has to be set up a time, t
7
, before the
SCLK rising edge as the part samples the input data on the
SCLK rising edge in this case. The POLARITY pin may be
used to change the SCLK edge which the data is sampled on
and clocked out on. If resetting the interface is required, the
SYNC
must be taken high and then low.
Mode 3 (QSPI Interface Mode)
Figure 36 shows the timing diagram for
Interface Mode 3. In
this mode the DSP is the master and the part is the slave. Here
the
SYNC
input is edge triggered from high to low, and the 16
clock pulses are counted from this edge. Since the clock pulses
are counted internally then the
SYNC
signal does not have to go
t
3
= –0.4 t
MIN (NONCONTINUOUS SCLK) –/+0.4 t
MIN/MAX (CONTINUOUS SCLK),
t
6
= 75/115 MAX (5V/3V), t
= 40/60ns
MIN (5V/3V), t
= 20/30
MIN (5V/3V),
t
11
= 20/30 MIN (NONCONTINUOUS SCLK) (5V/3V), (30/50)/0.4 t
SCLK
= ns
MIN/MAX (CONTINUOUS SCLK) (5V/3V)
DOUT (O/P)
SCLK (I/P)
SYNC
(I/P)
DB0
t
3
t
8
t
10
t
9
t
5
DIN (I/P)
THREE-
STATE
THREE-
STATE
t
11
t
6
t
6
t
8
1
6
2
3
4
5
16
POLARITY PIN
LOGIC HIGH
t
12
DB11
DB10
DB15
DB14
DB13
DB12
DB0
DB11
DB10
DB15
DB14
DB13
DB12
t
7
Figure 35. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation with DIN Input, DOUT Output and
SYNC
Input
(SM1 = SM2 = 0)
t
7
DOUT (O/P)
SCLK (I/P)
SYNC
(I/P)
DB0
t
3
t
8
t
10
t
9
t
5
DIN (I/P)
THREE-
STATE
THREE-
STATE
t
11
t
6
t
6
t
8
1
6
2
3
4
5
16
POLAR PIN
LOGIC HIGHITY
t
12
DB11
DB10
DB15
DB14
DB13
DB12
DB0
DB11
DB10
DB15
DB14
DB13
DB12
t
3
= –0.4 t
MIN (NONCONTINUOUS SCLK) –/+0.4 t
MIN/MAX (CONTINUOUS SCLK),
t
6
= 75/115 MAX (5V/3V), t
7
= 40/60ns
MIN (5V/3V), t
8
= 20/30
MIN (5V/3V),
t
11
= 20/30 MIN (5V/3V)
Figure 36. QSPI Mode 3 Timing Diagram for Read/Write Operation with
SYNC
Input Edge Triggered (SM1 = 0, SM2 = 1)
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