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參數資料
| 型號： | AD7853LAR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數： | 26/34頁 |
| 文件大?。?/td> | 350K |
| 代理商： | AD7853LAR |
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REV. B
–26–
AD7853/AD7853L
The most important point about these two modes of operation
mode is that
the result of the current conversion is clocked
out during the same conversion
and a write to the part dur-
ing this conversion is for the next conversion. The arrangement
is shown in Figure 37. Figure 38 and Figure 39 show more
detailed timing for the arrangement of Figure 37.
WRITE N+1
CONVERSION N
READ N
5
m
s
WRITE N+2
CONVERSION N+1
READ N+1
WRITE N+3
CONVERSION N+2
READ N+2
5
m
s
THE CONVERSION RESULT DUE TO
WRITE N+1 IS READ HERE
5
m
s
Figure 37.
t
1
CONVST
(I/P)
SCLK
(O/P)
CONVERSION ENDS
4.6
m
s LATER
SERIAL READ
AND WRITE
OPERATIONS
OUTPUT SERIAL SHIFT
REGISTER IS RESET
READ OPERATION
SHOULD END 500ns
PRIOR TO NEXT RISING
EDGE OF
CONVST
400ns MIN
BUSY
(O/P)
SYNC
(O/P)
CONVERSION IS INITIATED
AND TRACK/HOLD GOES
INTO HOLD
t
1
= 100ns MIN
t
CONVERT
= 4.6
m
s
Figure 38. Mode 4, 5 Timing Diagram (SM1 = 1, SM2 = 1
and 0)
In Figure 38 the first point to note is that the BUSY,
SYNC
,
and SCLK are all outputs from the AD7853/AD7853L with the
CONVST
being the only input signal. Conversion is initiated
with the
CONVST
signal going low. This
CONVST
falling
edge also triggers the BUSY to go high. The
CONVST
signal
rising edge triggers the
SYNC
to go low after a short delay
(0.5 t
CLKIN
to 1.5 t
CLKIN
typically) after which the SCLK will
clock out the data on the DOUT pin during conversion. The
data on the DIN pin is also clocked in to the AD7853/AD7853L
by the same SCLK for the next conversion. The read/write
operations must be complete after sixteen clock cycles (
which
takes
4.6
μ
s approximately from the rising edge of
CONVST
assum-
ing a
4
MHz CLKIN
). At this time the conversion will be com-
plete, the
SYNC
will go high, and the BUSY will go low. The
next falling edge of the
CONVST
must occur at least 400 ns
after the falling edge of BUSY to allow the track/hold amplifier
adequate acquisition time as shown in Figure 38. This gives a
throughput time of 5
μ
s. The maximum throughput rate in this
case is 200 kHz (AD7853) and 100 kHz (AD7853L).
In these interface modes the part is now the master and the DSP
is the slave. Figure 39 is an expansion of Figure 38. The
AD7853/AD7853L will ensure
SYNC
goes low after the rising
edge C of the continuous SCLK (Interface Mode 5) in Figure
39. Only in the case of a noncontinuous SCLK (Interface Mode
4) will the time t
4
apply. The first data bit is clocked out from
the falling edge of
SYNC
. The SCLK rising edge clocks out all
subsequent bits on the DOUT pin. The input data present on
the DIN pin is clocked in on the rising edge of the SCLK. The
POLARITY pin may be used to change the SCLK edge which
the data is sampled on and clocked out on. The
SYNC
will go
high after the 16th SCLK rising edge and before the falling edge
D of the continuous SCLK in Figure 39. This ensures the part
will not clock in an extra bit from the DIN pin or clock out an
extra bit on the DOUT pin.
If the user has control of the
CONVST
pin but does not want to
exercise it for every conversion, the control register may be used
to start a conversion. Setting the CONVST bit in the control
register to 1 starts a conversion. If the user does not have con-
trol of the
CONVST
pin, a conversion should not be initiated
by writing to the control register. The reason for this is that the
user may get “locked out” and not be able to perform any fur-
ther write/read operations. When a conversion is started by
writing to the control register, the
SYNC
goes low and read/
write operations take place while the conversion is in progress.
However, once the conversion is complete, there is no way of
writing to the part unless the
CONVST
pin is exercised. The
CONVST
signal triggers the
SYNC
signal low which allows
read/write operations to take place.
SYNC
must be low to per-
form read/write operations. The
SYNC
is triggered low by the
CONVST
signal rising edge or setting the CONVST bit in the
control register to 1. Therefore if there is not full control of the
CONVST
pin the user may end up getting “locked out.”
DOUT (O/P)
SCLK (O/P)
SYNC
(O/P)
DIN (I/P)
t
8
POLARITY PIN
LOGIC HIGH
1
2
3
t
10
4
5
6
16
DB0
DB15
DB14
DB13
DB12
DB11
DB10
DB0
THREE-
STATE
THREE-
STATE
DB11
DB10
DB14
DB13
DB12
t
6
t
9
t
12
t
11A
t
4
t
5
DB15
t
8
t
7
C
D
t
4
= 0.6t
(NONCONTINUOUS SCLK), t
= 75/115 MAX (5V/3V),
t
7
= 40/60ns
MIN (5V/3V), t
8
= 20/30
MIN (5V/3V), t
11A
= 50ns MAX
Figure 39. Timing Diagram for Read/Write with
SYNC
Output and SCLK Output (Continuous and Noncontinuous)
(i.e., Operating Mode Numbers 4 and 5, SM1 = 1, SM2 = 1 and 0)
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