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參數資料
| 型號： | AD7853LAR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數： | 4/34頁 |
| 文件大?。?/td> | 350K |
| 代理商： | AD7853LAR |
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REV. B
–4–
AD7853/AD7853L
TIMING SPECIFICATIONS
1
Limit at T
MIN
, T
MAX
(A, B Versions)
Parameter
5 V
f
CLKIN2
500
4
1.8
1
f
SCLK3
4
f
CLKIN
t
14
100
t
2
50
t
CONVERT
4.6
10 (18)
t
3
–0.4 t
SCLK
7
0.4 t
SCLK
t
4
0.6 t
SCLK
t
55
50
t
5A5
50
t
65
75
t
7
40
t
8
20
t
96
0.4 t
SCLK
t
106
0.4 t
SCLK
t
11
30
30/0.4 t
SCLK
t
50
t
11A
50
t
13
90
t
148
50
t
15
2.5 t
CLKIN
t
16
2.5 t
CLKIN
t
CAL9
31.25
3 V
Units
Description
500
4
1.8
1
4
f
CLKIN
100
90
4.6
10 (18)
–0.4 t
SCLK
7
0.4 t
SCLK
0.6 t
SCLK
90
90
115
60
30
0.4 t
SCLK
0.4 t
SCLK
50
50/0.4 t
SCLK
50
50
130
90
2.5 t
CLKIN
2.5 t
CLKIN
31.25
kHz min
MHz max
MHz max
MHz max
MHz max
MHz max
ns min
ns max
μ
s max
μ
s max
ns min
ns min/max
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ns max
ms typ
Master Clock Frequency
L Version, 0
°
C to +70
°
C, B Grade Only
L Version, –40
°
C to +85
°
C
Interface Modes 1, 2, 3 (External Serial Clock)
Interface Modes 4, 5 (Internal Serial Clock)
CONVST
Pulsewidth
CONVST
↓
to BUSY
↑
Propagation Delay
Conversion Time = 18 t
CLKIN
L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 t
CLKIN
SYNC
↓
to SCLK
↓
Setup Time (Noncontinuous SCLK Input)
SYNC
↓
to SCLK
↓
Setup Time (Continuous SCLK Input)
SYNC
↓
to SCLK
↓
Setup Time. Interface Mode 4 Only
Delay from
SYNC
↓
until DOUT 3-State Disabled
Delay from
SYNC
↓
until DIN 3-State Disabled
Data Access Time After SCLK
↓
Data Setup Time Prior to SCLK
↑
Data Valid to SCLK Hold Time
SCLK High Pulsewidth (Interface Modes 4 and 5)
SCLK Low Pulsewidth (Interface Modes 4 and 5)
SCLK
↑
to
SYNC
↑
Hold Time (Noncontinuous SCLK)
(Continuous SCLK) Does Not Apply to Interface Mode 3
SCLK
↑
to
SYNC
↑
Hold Time
Delay from
SYNC
↑
until DOUT 3-State Enabled
Delay from SCLK
↑
to DIN Being Configured as Output
Delay from SCLK
↑
to DIN Being Configured as Input
CAL
↑
to BUSY
↑
Delay
CONVST
↓
to BUSY
↑
Delay in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent
(125013 t
CLKIN
)
Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (111114 t
CLKIN
)
System Offset Calibration Time, Master Clock Dependent
(13899 t
CLKIN
)
t
CAL19
27.78
27.78
ms typ
t
CAL29
3.47
3.47
ms typ
NOTES
Descriptions that refer to SCLK
↑
(rising) or SCLK
↓
(falling) edges here are with the POLARITY pin HIGH. For the POLARITY pin LOW then the opposite edge of
SCLK will apply.
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V. See
Table X and timing diagrams for different interface modes and calibration.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
For Interface Modes 1, 2, 3 the SCLK max frequency will be 4 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be f
.
4
The
CONVST
pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different
CONVST
pulsewidth will apply (see Power-
Down section).
5
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6
For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 t
= 0.5 t
.
7
t
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
12
, quoted in the timing characteristics is the true bus relin-
quish time of the part and is independent of the bus loading.
8
t
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part
in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will
not occur.
9
The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8/1 MHz master clock.
Specifications subject to change without notice.
(AV
DD
= DV
DD
= +3.0 V to +5.5 V; f
CLKIN
= 4 MHz for AD7853 and 1.8/1 MHz for AD7853L; T
A
= T
MIN
to
T
MAX
, unless otherwise noted)
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