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參數(shù)資料
| 型號： | AD7992BRM-0 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, 12-Bit ADC with I2C Compatible Interface in 10-Lead MSOP |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MO-187-BA, MSOP-10 |
| 文件頁數(shù)： | 16/21頁 |
| 文件大小： | 266K |
| 代理商： | AD7992BRM-0 |
AD7992
–16–
REV. PrH
PRELIMINARY TECHNICAL DATA
WRITING TO THE AD7992
Depending on the register being written to, there are two
different writes for the AD7992.
Writing to the Address Pointer Register for a Subse-
quent Read
In order to read from a particular register, the Address
Pointer register must first contain the address of that reg-
ister. If it does not, the correct address must be written to
the Address pointer register by performing a single-byte
write operation, as shown in Figure 10. The write opera-
tion consists of the serial bus address followed by the ad-
dress pointer byte. No data is written to any of the data
registers. A read operation is subsequently performed to
read the register of interest.
Writing a Single Byte of Data to the Configuration Reg-
ister or Cycle Register
The Configuration Register and Cycle Register are both
8-bit registers, so only one byte of data can be written to
each. Writing a single byte of data to one of these registers
consists of the serial bus address, the chosen data register
address written to the Address Pointer Register, followed
by the data byte written to the selected data register. This
is illustrated in Figure 11.
Writing a Single Byte of Data to a Limit Register
Each of the four Limit Registers are 12-bit registers, so
two bytes of data are required to write a value to any one
of them. Writing two bytes of data to one of these registers
consists of the serial bus address, the chosen Limit Regis-
ter address written to the Address Pointer Register, fol-
lowed by two data bytes written to the selected data
register. This is illustrated in Figure 12.
SERIAL INTERFACE
Control of the AD7992 is carried out via the I
2
C-compat-
ible serial bus. The AD7992 is connected to this bus as a
slave device, under the control of a master device, e.g. the
processor.
SERIAL BUS ADDRESS
Like all I
2
C-compatible devices, the AD7992 has a 7-bit
serial address. The three MSBs of this address for the
AD7992 are set to 010. The AD7992 comes in two ver-
sions, the AD7992-0 to AD7992-1. The two versions have
three different I
2
C addresses available which are selected
by either tying the Address Select pin, AS, to GND, to
V
DD
or letting the pin float (see Table I). By giving dif-
ferent addresses for the two versions, up to five AD7992
devices can be connected to a single serial bus, or the
addresses can be set to avoid conflicts with other devices
on the bus.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
START condition, defined as a high to low transition
on the serial data line SDA whilst the serial clock line
SCL remains high. This indicates that an address/data
stream will follow. All slave peripherals connected to
the serial bus respond to the START condition, and
shift in the next 8 bits, consisting of a 7-bit address
(MSB first) plus a R/
W
bit, which determines the di-
rection of the data transfer, i.e. whether data will be
written to or read from the slave device.
The peripheral whose address corresponds to the trans-
mitted address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the Acknowledge Bit. All other devices on the
bus now remain idle whilst the selected device waits for
data to be read from or written to it. If the R/
W
bit is a
0 then the master will write to the slave device. If the
R/
W
bit is a 1 the master will read from the slave de-
vice.
2. Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an Acknowledge Bit
from the receiver of data. Transitions on the data line
must occur during the low period of the clock signal
and remain stable during the high period, as a low to
high transition when the clock is high may be inter-
preted as a STOP signal.
Figure 10. Writing to the Address Pointer Register to se-
lect a register for a subsequent Read operation
3. When all data bytes have been read or written, stop
conditions are established. In WRITE mode, the master
will pull the data line high during the 10th clock pulse
to assert a STOP condition. In READ mode, the mas-
ter device will pull the data line high during the low
period before the 9th clock pulse. This is known as No
Acknowledge. The master will then take the data line
low during the low period before the 10th clock pulse,
then high during the 10th clock pulse to assert a STOP
condition.
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix
read and write in one operation, because the type of opera-
tion is determined at the beginning and cannot subse-
quently be changed without starting a new operation.
SDA
ACK. BY
AD7992
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
ACK. BY
AD7992
1
9
1
9
C4
C3
C2
P2
P1
P0
R/
A0
A1
A2
A3
0
0
SCL
STOP BY
MASTER
1
C1
P3
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7992BRM-0REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 188ksps 12-bit Serial 10-Pin MSOP T/R |
| AD7992BRM-1 | 制造商:Analog Devices 功能描述:ADC Single SAR 188ksps 12-bit Serial 10-Pin MSOP 制造商:Rochester Electronics LLC 功能描述:2-CHANNEL, 12-BIT ADC WITH 12C ITF I.C. - Bulk |
| AD7992BRM-1REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 188ksps 12-bit Serial 10-Pin MSOP T/R |
| AD7992BRMZ-0 | 功能描述:IC ADC 12BIT 2CHAN I2C 10MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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