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參數資料
| 型號： | AD7992BRM-0 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, 12-Bit ADC with I2C Compatible Interface in 10-Lead MSOP |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MO-187-BA, MSOP-10 |
| 文件頁數： | 20/21頁 |
| 文件大小： | 266K |
| 代理商： | AD7992BRM-0 |
AD7992
–20–
REV. PrH
PRELIMINARY TECHNICAL DATA
Mode 2 -
This mode allows a conversion to be automatically initi-
ated anytime a read operation occurs. In order to use this
mode the command bits C2 - C1 in the Address Pointer
Register shown in Table II must be programmed. The
command bits C4 and C3 are not used and should contain
zeros at all times.
To select a channel for conversion in this mode, set the
corresponding channel command bits in the Address
Pointer byte, see Table XIII. To select both Analog inout
channels for conversion in this mode set both C1 and C2
to 1. When all four command bits are 0 then this mode is
not in use.
Figure 13 illustrates a two byte read operation from the
Conversion Result Register. First ensure that the Address
pointer is pointing to the conversion result register. When
the contents of the Address Pointer Register are being
loaded, if the command bits C2 or C1 are set then the
AD7992 will begin to power up and convert upon the
selected channel(s), power-up will begin on the fifth SCL
falling edge of the Address Point Byte, see point A Figure
17. Table XIII shows the channel selection in this mode
via the command bits, C1 and C2 in the Address Pointer
Register. The wake-up and conversion time together
should take approximately 3
μ
s, and the conversion begins
when the last Command bit, C1 has been clocked in mid-
way through the write to the Address Pointer Register.
Following this, the AD7992 must be addressed again to
tell it that a read operation is required. The read then
Figure 17. Mode 2 Operation
Table XIII. Channel Selection in Mode 2
C2
C1
Analog Input Channel
0
0
No Conversion
0
1
Conversion on V
IN
1
Conversion on V
IN
2
Conversion on V
IN
1 followed by Converion
on V
IN
2
1
0
1
1
takes place from the Conversion Result register. This read
will access the result from the conversion selected via the
command bits. If the Command bits C2, C1 were set to
1,1, then a four byte read would be necessary. The first
read accesses the data from the conversion on V
IN
1. While
this read takes place, a converion occurs on V
IN
2. The
second read will access this data from V
IN
2. Figure 18
illustrates how this mode operates.
After the conversion result has been read and if further
read bytes are issued the ADC will continuously convert
on the selected input channel(s). This has the effect of
increasing the overall throughput rate of the ADC.
When operating the AD7992-1 in Mode2 with Hs-Mode,
3.4 MHz SCL, the conversion may not be complete be-
fore the master tries to read the conversion result, if this is
the case the AD7992-1 will hold the SCL line low after
the read address during the ACK clock, until the conver-
sion is complete. When the conversion is complete the
AD7992-1 will release the SCL line and the master can
then read the conversion result.
9
1
1
A
SCL
9
S
7-BIT ADDRESS
W
A COMMAND/ADDRESS POINT BYTE
A
SDA
Sr
7-BIT ADDRESS
R
A
FIRST DATA BYTE (MSBs)
A
SECOND DATA BYTE (LSBs)
SDA
1
1
9
SCL
9
9
Sr/
P
8
ACK BY
AD7992
ACK BY
AD7992
ACK BY
AD7992
ACK BY
MASTER
NACK BY
MASTER
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