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參數資料
| 型號： | AD7992BRM-0 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, 12-Bit ADC with I2C Compatible Interface in 10-Lead MSOP |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MO-187-BA, MSOP-10 |
| 文件頁數： | 21/21頁 |
| 文件大小： | 266K |
| 代理商： | AD7992BRM-0 |
AD7992
–21–
REV. PrH
PRELIMINARY TECHNICAL DATA
Mode 3 - Automatic Cycle Mode
An automatic conversion cycle can be selected and enabled
by writing a value to the Cycle Timer Register. A conver-
sion cycle interval can be set up on the AD7992 by pro-
gramming the relevant bits in the 3-bit Cycle Timer
Register as decoded in Table XIIb. When the Cycle
Timer register is programmed with any configuration
other than all 0’s, a conversion will take place every X ms,
depending on the configuration of these bits in the Cycle
Timer Register. There are 7 different cycle time intervals
to choose from as shown in Table XIIb. Once the conver-
sion has taken place the part powers down again until the
next conversion occurs. To exit this mode of operation the
user must program the Cycle Timer Register to contain
all 0’s. For cycle interval options see Table XIIb Cycle
Timer Intervals.
Figure 18. Mode 2 Sequence Operation
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
10-Lead MSOP (RM-10)
0.0197 (0.50)
BSC
0.120 (3.05)
0.112 (2.85)
0.122 (3.10)
0.114 (2.90)
10
6
5
1
0.199 (5.05)
0.187 (4.75)
PIN
1
0.122 (3.10)
0.114 (2.90)
0.012 (0.30)
0.006 (0.15)
0.037 (0.94)
0.031 (0.78)
SEATING
PLANE
0.043 (1.10)
MAX
0.006 (0.15)
0.002 (0.05)
0.028 (0.70)
0.016 (0.40)
0.009 (0.23)
0.005 (0.13)
6
0
o
0.120 (3.05)
0.112 (2.85)
o
To select channel(s) for operation in the cycle mode set
the corresponding channel(s) bits, D5 and D4, in the
Configuration Register. If both D5 and D4 are set to 1 in
the Configuration register, the ADC will automatically
cycle through the Channels, starting with the lowest chan-
nel and working its way up through the sequence. Once
the sequence is complete the ADC will start converting on
the lowest channel again, continuing to loop through the
sequence until the Cycle timer register contents are set to
all 0’s. This mode is useful for monitoring signals, e.g.
battery voltage, temperature etc, alerting only when the
limits are violated.
9
1
1
A
SCL
9
S
7-BIT ADDRESS
W
A
COMMAND/ADDRESS POINT BYTE
A
SDA
FIRST DATA BYTE (MSBs)
A
SECOND DATA BYTE (LSBs)
A
Sr
7-BIT ADDRESS
R
A
SDA
9
9
1
1
SCL
9
8
ACK BY
AD7992
ACK BY
AD7992
ACK BY
AD7992
ACK BY
MASTER
FIRST DATA BYTE (MSBs)
A
SECOND DATA BYTE (LSBs)
ACK BY
MASTER
ACK BY
MASTER
9
9
RESULT FROM CH1
RESULT FROM CH2
A/
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