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參數資料
| 型號： | AD7992BRM-0 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, 12-Bit ADC with I2C Compatible Interface in 10-Lead MSOP |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MO-187-BA, MSOP-10 |
| 文件頁數： | 17/21頁 |
| 文件大小： | 266K |
| 代理商： | AD7992BRM-0 |
AD7992
–17–
REV. PrH
PRELIMINARY TECHNICAL DATA
Figure 11. Single Byte Write Sequence
Figure 12. Two Byte Write Sequence
READING DATA FROM THE AD7992
Reading data from the AD7992 is a one or two byte op-
eration. Reading back the contents of the Configuration
Register, Alert Status Register or the Cycle Timer Regis-
ter is a single byte read operation as shown in Figure 13.
This assumes the particular register address has previously
been set up by a single byte write operation to the Address
Pointer Register, Figure 10. Once the register address has
been set up, any number of reads can subsequently be
performed from that particular register without having to
write to the Address Pointer Register again. If a read from
a different register is required, then the relevant register
address will have to be written to the Address Pointer
Register and again any number of reads from this register
may then be performed.
Reading data from the Conversion Result Register,
DATA
HIGH
Registers, DATA
LOW
Registers or Hysteresis
Registers is a two byte operation as shown in Figure 14.
The same rules apply for a two byte read as a single byte
read.
ALERT/BUSY PIN
The ALERT/BUSY may be configured as an Alert or
Busy ouput as shown in Table VI.
SMBus ALERT
The AD7992 ALERT output is an SMBus interrupt line
for devices that want to trade their ability to master for an
extra pin. The AD7992 is a slave only device and uses the
SDA
ACK. BY
AD7992
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
ACK. BY
AD7992
1
9
1
9
C4
C3
C2
P2
P1
P0
R/
A0
A1
A2
A3
0
0
SCL
1
C1
P3
9
1
9
D7
D6
D5
D2
D1
D0
D4
D3
STOP BY
MASTER
ACK. BY
AD7992
FRAME 3
DATA BYTE
SCL (CONTINUED)
SDA (CONTINUED)
SDA
ACK. BY
AD7992
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
ACK. BY
AD7992
1
9
1
9
C4
C3
C2
P2
P1
P0
R/
A0
A1
A2
A3
0
0
SCL
1
C1
P3
9
1
9
D7
D6
D5
D2
D1
D0
D4
D3
STOP BY
MASTER
ACK. BY
AD7992
LEAST SIGNIFICANT DATA BYTE
SCL (CONTINUED)
SDA (CONTINUED)
9
1
0
0
0
D10
D9
D8
0
D11
STOP BY
MASTER
ACK. BY
AD7992
MOST SIGNIFICANT DATA BYTE
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