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參數資料
| 型號： | AD9848 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processors with Integrated Timing Driver |
| 中文描述： | CCD信號處理器集成時序驅動 |
| 文件頁數： | 19/36頁 |
| 文件大小： | 347K |
| 代理商： | AD9848 |
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REV. 0
AD9848/AD9849
–19–
PRECISION TIMING
HIGH-SPEED TIMING
GENERATION
The AD9848 and AD9849 generate flexible high-speed timing
signals using the
Precision Timing
core. This core is the founda-
tion for generating the timing used for both the CCD and the
AFE; the reset gate RG, horizontal drivers H1–H4, and the
SHP/SHD sample clocks. A unique architecture makes it
routine for the system designer to optimize image quality, by
providing precise control over the horizontal CCD readout
and the AFE correlated double sampling.
Timing Resolution
The
Precision Timing
core uses a 1X master clock input (CLI) as
a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 4 illustrates how the internal timing core
divides the master clock period into 48 steps or edge positions.
Therefore, the edge resolution of the
Precision Timing
core is
(t
CLI
/48). For more information on using the CLI input, see the
Application Information section.
High Speed Clock Programmability
Figure 5 shows how the high-speed clocks RG, H1–H4, SHP,
and SHD are generated. The RG pulse has programmable rising
and falling edges, and may be inverted using the polarity control.
The horizontal clocks H1 and H3 have programmable rising and
falling edges, and polarity control. The H2 and H4 clocks are
always inverses of H1 and H3 respectively. Table II summarizes
the high-speed timing registers and their parameters.
The edge location registers are 6 bits wide, but there are only
48 valid edge locations available. Therefore, the register values
are mapped into four quadrants, with each quadrant containing
12 edge locations. Table III shows the correct register values
for the corresponding edge locations. Figure 6 shows the range
and default locations of the high-speed clock signals.
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH-SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
t
CLIDLY = 6 ns TYP).
P[0]
P[48]=P[0]
P[12]
P[24]
P[36]
1 PIXEL
PERIOD
...
...
CLI
t
CLIDLY
POSITION
Figure 4. High-Speed Clock Resolution From CLI Master Clock Input
H1/H3
H2/H4
CCD SIGNAL
RG
(1)
(2)
(3)
(4)
(5)
(6)
NOTES
PROGRAMMABLE CLOCK POSITIONS:
(1) RG RISING EDGE AND (2) FALLING EDGE
(3) SHP AND (4) SHD SAMPLE LOCATION
(5) H1/H3 RISING EDGE POSITION AND (6) FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3)
Figure 5. High-Speed Clock Programmable Locations
相關PDF資料 |
PDF描述 |
|---|---|
| AD9849 | CCD Signal Processors with Integrated Timing Driver |
| AD9849KST | CCD Signal Processors with Integrated Timing Driver |
| AD9851 | CMOS 180 MHz DDS/DAC Synthesizer |
| AD9852 | CMOS 300MHz Complete-DDS Synthesizer |
| AD9853 | Programmable Digital QPSK/16-QAM Modulator(可編程數字的四相移鍵控/16-正交幅度調制的調節器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9848AKST | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V/3.3V 48-Pin LQFP 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V 48LQFP - Bulk 制造商:Rochester Electronics LLC 功能描述:10 BIT 20 MSPS CCD SIGNAL PROCESSOR - Tape and Reel |
| AD9848AKSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V/3.3V 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V 48LQFP - Tape and Reel |
| AD9848AKSTZ | 制造商:Analog Devices 功能描述: |
| AD9848AKSTZRL | 制造商:Analog Devices 功能描述: |
| AD9848KST | 制造商:Rochester Electronics LLC 功能描述:10 BIT 18 MSPS 3V AFE & T - Bulk |
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