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參數資料
| 型號： | AD9848 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processors with Integrated Timing Driver |
| 中文描述： | CCD信號處理器集成時序驅動 |
| 文件頁數： | 22/36頁 |
| 文件大小： | 347K |
| 代理商： | AD9848 |
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REV. 0
AD9848/AD9849
–22–
HORIZONTAL CLAMPING AND BLANKING
The AD9848/AD9849’s horizontal clamping and blanking
pulses are fully programmable to suit a variety of applications.
As with the vertical timing generation, individual sequences are
defined for each signal, which are then organized into multiple
regions during image readout. This allows the dark pixel clamp-
ing and blanking patterns to be changed at each stage of the
readout, in order to accommodate different image transfer tim-
ing and high-speed line shifts.
Individual CLPOB, CLPDM, and PBLK Sequences
The AFE horizontal timing consists of CLPOB, CLPDM, and
PBLK, as shown in Figure 9. These three signals are indepen-
dently programmed using the registers in Table IV. SPOL is the
start polarity for the signal, and TOG1 and TOG2 are the first
and second toggle positions of the pulse. All three signals are
active low, and should be programmed accordingly. Up to four
individual sequences can be created for each signal.
Individual HBLK Sequences
The HBLK programmable timing shown in Figure 10 is similar
to CLPOB, CLPDM, PBLK. However, there is not start polar-
ity control. Only the toggle positions are used, to designate the
start and the stop positions of the blanking period. Additionally,
there is a polarity control HBLKMASK which designates the
polarity of the horizontal clock signals H1 – H4 during the blank-
ing period. Setting HBLKMASK high will set H1 = H3 = low
and H2 = H4 = high during the blanking, as shown in Figure
11. Up to four individual sequences are available for HBLK.
(3)
(2)
(1)
HD
CLPOB
CLPDM
PBLK
. . .
NOTES
PROGRAMMABLE SETTINGS:
(1) START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)
(2) FIRST TOGGLE POSITION
(3) SECOND TOGGLE POSITION
. . .
CLAMP
CLAMP
Figure 9. Clamp and Preblank Pulse Placement
(2)
(1)
HD
HBLK
. . .
NOTES
PROGRAMMABLE SETTINGS:
(1) FIRST TOGGLE POSITION = START OF BLANKING
(2) SECOND TOGGLE POSITION = END OF BLANKING
. . .
BLANK
BLANK
Figure 10. Horizontal Blanking (HBLK) Pulse Placement
Table IV. CLPOB, CLPDM, PBLK Individual Sequence Parameters
Register Name
Length
Range
Description
SPOL
TOG1
TOG2
1b
12b
12b
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
Starting Polarity of Clamp and Blanking Pulses for Sequences 0–3
First Toggle Position within the Line for Sequences 0–3
Second Toggle Position within the Line for Sequences 0–3
Table V. HBLK Individual Sequence Parameters
Register Name
Length
Range
Description
HBLKMASK
HBLKTOG1
HBLKTOG2
1b
12b
12b
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
Masking Polarity for H1 for Sequences 0–3 (0 = H1 Low, 1 = H1 High)
First Toggle Position within the Line for Sequences 0–3
Second Toggle Position within the Line for Sequences 0–3
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9848AKST | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V/3.3V 48-Pin LQFP 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V 48LQFP - Bulk 制造商:Rochester Electronics LLC 功能描述:10 BIT 20 MSPS CCD SIGNAL PROCESSOR - Tape and Reel |
| AD9848AKSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V/3.3V 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V 48LQFP - Tape and Reel |
| AD9848AKSTZ | 制造商:Analog Devices 功能描述: |
| AD9848AKSTZRL | 制造商:Analog Devices 功能描述: |
| AD9848KST | 制造商:Rochester Electronics LLC 功能描述:10 BIT 18 MSPS 3V AFE & T - Bulk |
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