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參數(shù)資料
| 型號(hào)： | AD9848 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processors with Integrated Timing Driver |
| 中文描述： | CCD信號(hào)處理器集成時(shí)序驅(qū)動(dòng) |
| 文件頁(yè)數(shù)： | 29/36頁(yè) |
| 文件大小： | 347K |
| 代理商： | AD9848 |
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REV. 0
AD9848/AD9849
–29–
COLOR
STEERING
CONTROL
4:1
MUX
3
GAIN0
GAIN1
GAIN2
GAIN3
PxGA
PxGA
STEERING
MODE
SELECTION
2
6
VD
HD
PxGA
GAIN
REGISTERS
CONTROL
REGISTER
BITS D0
–
D2
SHP/SHD
VGA
CDS
Figure 17. PxGA Block Diagram
R
Gr
R
Gr
Gb
B
Gb
B
R
Gr
R
Gr
Gb
B
Gb
B
GAIN0, GAIN1, GAIN0, GAIN1...
LINE0
GAIN2, GAIN3, GAIN2, GAIN3...
LINE1
GAIN0, GAIN1, GAIN0, GAIN1...
LINE2
CCD: PROGRESSIVE BAYER
MOSAIC SEPARATE COLOR
STEERING MODE
Figure 18a. CCD Color Filter Example: Progressive Scan
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
GAIN0, GAIN1, GAIN0, GAIN1...
LINE0
GAIN0, GAIN1, GAIN0, GAIN1...
LINE1
GAIN0, GAIN1, GAIN0, GAIN1...
LINE2
CCD: INTERLACED BAYER
EVEN FIELD
VD SELECTED COLOR
STEERING MODE
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
GAIN2, GAIN3, GAIN2, GAIN3...
LINE0
GAIN2, GAIN3, GAIN2, GAIN3...
LINE1
GAIN2, GAIN3, GAIN2, GAIN3...
LINE2
ODD FIELD
Figure 18b. CCD Color Filter Example: Interlaced
The same Bayer pattern can also be interlaced, and the VD
selected mode should be used with this type of CCD (see
Figure 18b). The Color Steering performs the proper multi-
plexing of the R, G, and B gain values (loaded into the
PxGA
gain registers), and is synchronized by the user with vertical
(VD) and horizontal (HD) sync pulses. For more detailed
information, see the
PxGA
Timing section. The
PxGA
gain
for each of the four channels is variable from –2 dB to +10 dB,
controlled in 64 steps through the serial interface. The
PxGA
gain curve is shown in Figure 19.
PxGA
GAIN REGISTER CODE
10
32
P
–
40
48
58
0
8
16
24
31
8
6
4
2
0
–
2
(011111)
(100000)
Figure 19. PxGA Gain Curve
Variable Gain Amplifier
The VGA stage provides a gain range of 2 dB to 36 dB, pro-
grammable with 10-bit resolution through the serial digital
interface. Combined with 4 dB from the
PxGA
stage, the total
gain range for the AD9848/AD9849 is 6 dB to 40 dB. The
minimum gain of 6 dB is needed to match a 1 V input signal
with the ADC full-scale range of 2 V. When compared to 1 V
full-scale systems (such as ADI’s AD9803), the equivalent gain
range is 0 dB to 34 dB.
The VGA gain curve is divided into two separate regions. When
the VGA Gain Register code is between 0 and 511, the curve
follows a (1 + x)/(1 – x) shape, which is similar to a “l(fā)inear-in-dB”
characteristic. From code 512 to code 1023, the curve follows a
“l(fā)inear-in-dB” shape. The exact VGA gain can be calculated for
any Gain Register value by using the following two equations:
Code Range
Gain Equation (dB)
0 – 511
512 – 1023
Gain
= 20 log
10
([658 +
code
]/[658 –
code
]) – 0.4
Gain
= (0.0354)(
code
) – 0.04
VGA GAIN REGISTER CODE
36
0
V
–
127
255
383
511
639
767
895
1023
30
24
18
12
6
0
Figure 20. VGA Gain Curve (Gain from PxGA Not
Included)
相關(guān)PDF資料 |
PDF描述 |
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| AD9849 | CCD Signal Processors with Integrated Timing Driver |
| AD9849KST | CCD Signal Processors with Integrated Timing Driver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9848AKST | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V/3.3V 48-Pin LQFP 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V 48LQFP - Bulk 制造商:Rochester Electronics LLC 功能描述:10 BIT 20 MSPS CCD SIGNAL PROCESSOR - Tape and Reel |
| AD9848AKSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V/3.3V 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V 48LQFP - Tape and Reel |
| AD9848AKSTZ | 制造商:Analog Devices 功能描述: |
| AD9848AKSTZRL | 制造商:Analog Devices 功能描述: |
| AD9848KST | 制造商:Rochester Electronics LLC 功能描述:10 BIT 18 MSPS 3V AFE & T - Bulk |
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