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參數(shù)資料
| 型號(hào)： | AD9853 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Programmable Digital QPSK/16-QAM Modulator(可編程數(shù)字的四相移鍵控/16-正交幅度調(diào)制的調(diào)節(jié)器) |
| 中文描述： | 可編程數(shù)字QPSK/16-QAM調(diào)制器（可編程數(shù)字的四相移鍵控/ 16 -正交幅度調(diào)制的調(diào)節(jié)器） |
| 文件頁數(shù)： | 26/31頁 |
| 文件大小： | 339K |
| 代理商： | AD9853 |
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AD9853
–26–
REV. A
around the constellation has simply been reversed. This effect
also holds true for the 16-QAM and D16-QAM constellations
shown in the respective I
×
COS – Q
×
SIN and I
×
COS + Q
×
SIN mappings shown in Figure 37.
DIRECT DIGITAL SYNTHESIZER FUNCTION
The direct digital synthesizer (DDS) block delivers the sine/cosine
carriers that are digitally modulated by the I/Q data paths. The
DDS function is frequency tuned via the control bus with a
32-bit tuning word. This allows the AD9853’s output carrier
frequency to be very precisely tuned while still providing output
frequency agility.
The equation relating output frequency of the AD9853 digital
modulator to the frequency tuning word (FTWORD) and the
reference clock (REFCLK) is given as:
f
OUT
= (
FTWORD
×
REFCLK
)/2
32
where:
f
OUT
and
REFCLK
frequencies are in Hz and
FTWORD
is a decimal number from 0 to (2
32
)/2
Example: Find the FTWORD for f
OUT
= 41 MHz and REFCLK
= 122.88 MHz
If f
OUT
= 41 MHz and REFCLK = 122.88 MHz, then:
FTWORD
= 556AAAAA
hex
Loading 556AAAAAh into control bus registers 16h–19h programs
the AD9853 for f
OUT
= 41 MHz, given a REFCLK frequency of
122.88 MHz.
D/A CONVERTER
Up to this point all the processing has been in the digital domain.
In order to pass the modulated signal onto the cable driver for
amplification to the levels required to drive the 75 ohm cable, a
digital-to-analog converter (DAC) is implemented. The DAC
needs to have good enough transient characteristics so as not to
add significant spurious in the spectrum. Typically the worst
spurs from the DAC are due to harmonics of the fundamental
signal and their aliases (please see the AD9850 complete-DDS
data sheet for a detailed explanation of aliased images). These
harmonics are worst case for the higher carrier frequencies. The
AD9853 contains a wideband 10-bit DAC which maintains
spurious-free dynamic range (SFDR) performance of –50 dBc
up to 42 MHz A
OUT
and –44 dBc up to 65 MHz A
OUT
.
The conversion process will produce aliased components at the
DAC output at n
×
f
CLOCK
±
f
CARRIER
(n = 1, 2, 3, ...). These
are typically filtered with an external RLC filter between the
DAC and the line driver amplifier. Again, it is important for this
analog filter to have a sufficiently flat gain and linear phase
response across the bandwidth of interest so as to avoid the
aforementioned modulation impairments. A relatively inexpen-
sive seventh order elliptical low-pass filter is sufficient to sup-
press the aliased components for HFC network applications.
The AD9853 provides true and complement outputs, Pins 24
and 25, which are current outputs. The full-scale output current
is set by the R
SET
resistor at Pin 18. The value of R
SET
for a
particular I
OUT
is determined using the following equation:
R
SET
= 32 (1.248
V
/
I
OUT
)
For example, if a full-scale output current of 20 mA is desired,
then R
SET
= 32(1.248/0.02), or approximately 2 k
. Every
doubling of the R
SET
value will halve the output current. Maxi-
mum output current is specified as 20 mA.
The full-scale output current range of the AD9853 is 5 mA–20mA,
with 10 mA being the optimal value for best spurious-free
dynamic range (SFDR). Full-scale output currents outside of
this range will degrade SFDR performance. SFDR is also slightly
affected by output matching, that is, for best SFDR, the two
outputs should be equally terminated.
The output load should be located as close as possible to the
AD9853 package to minimize stray capacitance and inductance.
The load may be a simple resistor to ground, an op amp cur-
rent-to-voltage converter, or a transformer-coupled circuit. It is
best not to attempt to directly drive highly reactive loads (such
as an LC filter). Driving an LC filter without a transformer
requires that the filter be doubly terminated for best performance,
that is, the filter input and output should both be resistively
terminated with the appropriate values. The parallel combina-
tion of the two terminations will determine the load that the
AD9853 will see for signals within the filter passband. For ex-
ample, a 50
terminated input/output low-pass filter will look
like a 25
load to the AD9853. The resistor at the filter input
will mask the reactive components of the LC filter and provide a
termination for signals outside the filter pass band.
The output compliance voltage of the AD9853 is –0.5 V to
+1.5 V. Any signal developed at the DAC output should not
exceed +1.5 V, otherwise, signal distortion will result. Further-
more, the signal may extend below ground as much as 0.5 V
without damage or signal distortion. The use of a transformer
with a grounded center-tap for common-mode rejection results
in signals at the AD9853 DAC output pins that are symmetrical
about ground.
As previously mentioned, by differentially combining the two
signals the user can provide some degree of common-mode
signal rejection. The amount of rejection is dependent upon
how closely the common-mode signals of each output are
matched in amplitude and phase. If the signals are exactly alike,
then ideally, there would be 100 percent rejection in a perfect
differential amplifier or combiner. A differential combiner might
consist of a transformer or an op amp. The object is to combine
or amplify only the difference between two signals and to reject
any common, usually undesirable, characteristic, such as 60 Hz
hum or “clock feed through” that is present on both input sig-
nals. The AD9853 true and complement outputs can be differ-
entially combined and, in fact, are configured as such on the
AD9853-XXPCB evaluation board. This evaluation board
utilizes a broadband 1:1 transformer with a grounded, center-
tapped primary to perform differential combining of the two
DAC outputs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9854 | CMOS 300MHz Quadrature Complete-DDS |
| AD9858TLPCB | 1 GSPS Direct Digital Synthesizer |
| AD9858BSV | 1 GSPS Direct Digital Synthesizer |
| AD9858PCB | 1 GSPS Direct Digital Synthesizer |
| AD9858 | 1 GSPS Direct Digital Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9853-45PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Programmable Digital OPSK/16-QAM Modulator |
| AD9853-65PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Programmable Digital OPSK/16-QAM Modulator |
| AD9853AS | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9854 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MHz Quadrature Complete-DDS |
| AD9854/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For IC Digital Synthesizer Single 制造商:Analog Devices 功能描述:Direct Digital Synthesizer IC (DDS) |
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