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參數(shù)資料
| 型號(hào)： | AD9853 |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 英文描述： | Programmable Digital QPSK/16-QAM Modulator(可編程數(shù)字的四相移鍵控/16-正交幅度調(diào)制的調(diào)節(jié)器) |
| 中文描述： | 可編程數(shù)字QPSK/16-QAM調(diào)制器（可編程數(shù)字的四相移鍵控/ 16 -正交幅度調(diào)制的調(diào)節(jié)器） |
| 文件頁(yè)數(shù)： | 6/31頁(yè) |
| 文件大小： | 339K |
| 代理商： | AD9853 |
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AD9853
–6–
REV. A
Table II. Control Register Functional Assignment
Register
Address
(Note 1)
00h
01h
DATA
D7
MSB
MSB
D6
Value of
K
(Message Length in Bytes) for
Reed-Solomon
Encoder, where 16
10
≤
K
≤
255
10
(Note 2)
The Number of Correctable Byte
LSB
Errors (t) for the
Reed-Solomon
Encoder
, where 0
≤
t
≤
10
10
.
For
t
= 0, the RS encoder is
effectively disabled.
Lower Eight Bits of Seed Value for 15-Bit Randomizer (Not Used for 6-Bit Randomizer)
Upper Seven Bits of Seed Value for 15-Bit Randomizer
– OR –
Seed Value for 6-Bit Randomizer (D1 not used in this case).
Preamble Length (L) where 0
≤
L
≤
96 Bits (Note 4)
D5
D4
D3
D2
D1
D0
LSB
(Note 3)
Randomizer
Insertion
Randomizer Length
00
2
= 6 Bit
01
2
= 15 Bit
10
2
= Randomizer OFF
11
2
= Randomizer OFF
0 = After RS
1 = Before RS
02h
03h
MSB
MSB
LSB
LSB
04h
05h
MSB
Modulation Mode
000
2
= QPSK , 001
2
= DQPSK, 010
2
= 16-QAM
011
2
= D16-QAM , 100
2
= FSK
The MSB of the preamble always resides in D7 of Address 11h and is the first preamble bit to be clocked out of the device during transmission of
a packet. Up to 96 bits of preamble are available as specified in Register 04h. Unused bits are
don’t care
for
L
< 96.
MSB
Preamble Data. (Note 5)
MSB
Interpolator #1: RATE
Rate Change Factor (
R
) where 3
10
≤
R
≤
31
10
MSB
Interpolator #2: RATE
Rate Change Factor (
R
) where 2
10
≤
R
≤
63
10
MSB
Interpolator #1: SCALE
LSB
06h
:
11h
12h
LSB
13h
LSB
14h
LSB
2
×
Multiplier
0 = OFF
1 = ON
LSB
15h
16h
:
19h
1Ah
:
1Dh
1Eh
5
1Fh
:
:
:
46h
47h
MSB
Interpolator #2: SCALE
Frequency Tuning Word #1
FSK Mode
: Specifies the “space” frequency (F0).
All Other Modes
: Specifies the carrier frequency.
Frequency Tuning Word #2
FSK Mode
: Specifies the “mark” frequency (F1).
(Addresses 1Ah–1Dh are only valid for FSK mode.)
10-Bit FIR End Tap Coefficient, a
0
<— —————————————Unused Bits ——————————————>
LSB
MSB
LSB
MSB
MSB-2
MSB
0
MSB-3
MSB-1
LSB
0
FIR Intermediate Tap Coefficients, a
1
– a
19
MSB-2
MSB
20
Spectrum
0 = I
×
Cos + Q
×
Sin
1 = I
×
Cos – Q
×
Sin
MSB-3
MSB-1
Digital Power
0 = Normal
1 = Shutdown
10-Bit FIR Center Tap Coefficient, a
20
<— —————————————Unused Bits ——————————————>
6
×
RefClk
PLL Mode
DAC Mode
0 = Off
0 = Awake
0 = Awake
1 = On
1 = Sleep
1 = Sleep
AD8320 Cable Driver Gain Control Byte (GCB)
The absolute gain, A
V
, of the AD8320 is given by:
A
V
= 0.316 + 0.077
×
GCB
(where 0
≤
GCB
≤
255
10
)
LSB
20
48h
(Note 6)
49h
(Note 7)
MSB
LSB
NOTES
1
The 8-bit
Register Address
is preceded by an 8-bit
Device Address,
which is given by
000001XY, where the value of Bits X and Y are determined as follows:
X
0
1
Voltage Applied to Pin 6
GND
+V
S
Y
0
1
Desired Register Function
WRITE
READ
2
This register must be loaded with a nonzero value even if the RS encoder has been
disabled by setting
T
= 0 in register 01h.
3
Unused regions are
don’t care
bit locations.
4
If a preamble is not used this register
must
be initialized to a value of 0 by the user.
5
Addresses 06h–011h and 1Eh–47h are write only.
6
Assertion of RESET (Pin 32) sets the contents of this register to 0.
7
Registers 0h–48h may be written to using a single register address followed by a
contiguous data sequence (see Figure 27). Register 49h, however, must be written to
individually; i.e., a separately addressed 8-bit data sequence.
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