
AD9858
AD9858—ELECTRICAL SPECIFICATIONS
Table 1. Unless otherwise noted, V
DD
= 3.3 V ± 5%, CPV
DD
= 5 V ± 5%, R
SET
= 2 k, C
PISET
= 2.4 k,
Reference Clock Frequency = 1 GHz.
Parameter
REF CLOCK INPUT CHARACTERISTICS
1, 2
Reference Clock Frequency Range (Divider Off)
Reference Clock Frequency Range (Divider On)
Duty Cycle @ 1 GHz
Input Capacitance
Input Impedance
Input Sensitivity
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Impedance
Voltage Compliance Range
Wideband SFDR (DC to Nyquist)
40 MHz F
OUT
100 MHz F
OUT
180 MHz F
OUT
360 MHz F
OUT
180 MHz F
OUT
(700 MHz REFCLK)
Narrow-Band SFDR3
3
40 MHz F
OUT
(±15 MHz)
40 MHz F
OUT
(±1 MHz)
40 MHz F
OUT
(±50 kHz)
100 MHz F
OUT
(±15 MHz)
100 MHz F
OUT
(±1 MHz)
100 MHz F
OUT
(±50 kHz)
180 MHz F
OUT
(±15 MHz)
180 MHz F
OUT
(±1 MHz)
180 MHz F
OUT
(±50 kHz)
360 MHz F
OUT
(±15 MHz)
360 MHz F
OUT
(±1 MHz)
360 MHz F
OUT
(±50 kHz)
180 MHz F
OUT
(±15 MHz) (700 MHz REFCLK)
180 MHz F
OUT
(±1 MHz) (700 MHz REFCLK)
180 MHz F
OUT
(±50 kHz) (700 MHz REFCLK)
OUTPUT PHASE NOISE CHARACTERISTICS (@ 103 MHz I
OUT
)
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
OUTPUT PHASE NOISE CHARACTERISTICS (@ 403 MHz I
OUT
)
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
Rev. A | Page 3 of 32
Temp
Full
Full
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
VI
VI
V
V
IV
VI
VI
VI
VI
VI
VI
VI
V
V
V
V
IV
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Min
10
20
42
–20
5
–10
AV
DD
– 1.5
52
Typ
50
3
1500
10
20
0.5
1
100
60
54
53
50
82
87
88
81
82
86
74
84
85
75
85
86
65
80
84
–147
–150
–152
–133
–137
–140
Max
1000
2000
58
+5
40
+10
15
1
1.5
AV
DD
+ 0.5
Unit
MHz
MHz
%
pF
dBm
Bits
mA
% FS
μA
LSB
LSB
k
V
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz