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參數資料
| 型號： | AD9859 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | 400 MSPS的10位，1.8伏的CMOS直接數字頻率合成 |
| 文件頁數： | 14/24頁 |
| 文件大小： | 574K |
| 代理商： | AD9859 |
AD9859
Control Register Bit Descriptions
Control Function Register No. 1 (CFR1)
Rev. 0 | Page 14 of 24
The CFR1 is used to control the various functions, features,
and modes of the AD9859. The functionality of each bit is
detailed below.
CFR1<31:27>: Not Used
CFR1<26>: Amplitude Ramp Rate Load Control Bit
CFR1<26> = 0 (default). The amplitude ramp rate timer is
loaded only upon timeout (timer == 1) and is not loaded due to
an I/O UPDATE input signal.
CFR1<26> = 1. The amplitude ramp rate timer is loaded upon
timeout (timer == 1) or at the time of an I/O UPDATE input signal.
CFR1<25>: Shaped On-Off Keying Enable Bit
CFR1<25> = 0 (default). Shaped on-off keying is bypassed.
CFR1<25> = 1. Shaped on-off keying is enabled. When enabled,
CFR1<24> controls the mode of operation for this function.
CFR1<24>: Auto Shaped On-Off Keying Enable Bit (Only Valid
when CFR1<25> Is Active High)
CFR1<24> = 0 (default). When CFR1<25> is active, a Logic 0
on CFR1<24> enables the manual shaped on-off keying opera-
tion. Each amplitude sample sent to the DAC is multiplied by
the amplitude scale factor. See the Shaped On-Off Keying sec-
tion for details.
CFR1<24> = 1. When CFR1<25> is active, a Logic 1 on
CFR1<24> enables the auto shaped on-off keying operation.
Toggling the OSK pin high causes the output scalar to ramp up
from zero scale to the amplitude scale factor at a rate deter-
mined by the amplitude ramp rate. Toggling the OSK pin low
causes the output to ramp down from the amplitude scale factor
to zero scale at the amplitude ramp rate. See the Shaped On-Off
Keying section for details.
CFR1<23>: Automatic Synchronization Enable Bit
CFR1<23> = 0 (default). The automatic synchronization feature
of multiple AD9859s is inactive.
CFR1<23> = 1. The automatic synchronization feature of mul-
tiple AD9859s is active. The device synchronizes its internal
synchronization clock (SYNC_CLK) to align to the signal pre-
sent on the SYNC_IN input. See the Synchronizing Multiple
AD9859s section for details.
CFR1<22>: Software Manual Synchronization of Multiple
AD9859s
CFR1<22> = 0 (default). The manual synchronization feature is
inactive.
CFR1<22> = 1. The software controlled manual synchroniza-
tion feature is executed. The SYNC_CLK rising edge is
advanced by one SYNC_CLK cycle and this bit is cleared. To
advance the rising edge multiple times, this bit needs to be set
for each advance. See the Synchronizing Multiple AD9859s sec-
tion for details.
CFR1<21:14>: Not Used
CFR1<13>: Auto-Clear Phase Accumulator Bit
CFR1<13> = 0 (default), the current state of the phase accumu-
lator remains unchanged when the frequency tuning word is
applied.
CFR1<13> = 1. This bit automatically synchronously clears
(loads 0s into) the phase accumulator for one cycle upon receiv-
ing an I/O UPDATE signal.
CFR1<12>: Sine/Cosine Select Bit
CFR1<12> = 0 (default). The angle-to-amplitude conversion
logic employs a COSINE function.
CFR1<12> = 1. The angle-to-amplitude conversion logic
employs a SINE function.
CFR1<11>: Not Used
CFR1<10>: Clear Phase Accumulator
CFR1<10> = 0 (default). The phase accumulator functions as
normal.
CFR1<10> = 1. The phase accumulator memory elements are
cleared and held clear until this bit is cleared.
CFR1<9>: SDIO Input Only
CFR1<9> = 0 (default). The SDIO pin has bidirectional opera-
tion (2-wire serial programming mode).
CFR1<9> = 1. The serial data I/O pin (SDIO) is configured as
an input-only pin (3-wire serial programming mode).
CFR1<8>: LSB First
CFR1<8> = 0 (default). MSB first format is active.
CFR1<8> = 1. The serial interface accepts serial data in LSB first
format.
CFR1<7>: Digital Power-Down Bit
CFR1<7> = 0 (default). All digital functions and clocks are active.
CFR1<7> = 1. All non-IO digital functionality is suspended,
lowering the power significantly.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9859/PCB | 制造商:Analog Devices 功能描述:NCO, 400MSPS 10 BIT, 1.8V CMOS DIRECT DGTL SYNTHESIZER - Bulk |
| AD9859/PCBZ | 功能描述:BOARD EVAL FOR AD9859 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9859/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit,1.8 V CMOS Direct Digital Synthesizer |
| AD9859_09 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9859YSV | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 10-Bit Serial 48-Pin TQFP EP 制造商:Analog Devices 功能描述:DDS 10BIT DAC 400MSPS SMD 9859 |
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