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參數資料
| 型號： | AD9859 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | 400 MSPS的10位，1.8伏的CMOS直接數字頻率合成 |
| 文件頁數： | 22/24頁 |
| 文件大小： | 574K |
| 代理商： | AD9859 |
AD9859
When the CFR1<3> bit is 0 and the PWRDWNCTL input pin is
high, the AD9859 is put into a fast recovery power-down mode.
In this mode, the digital logic and the DAC digital logic are
powered down. The DAC bias circuitry, PLL, oscillator, and
clock input circuitry is NOT powered down.
Rev. 0 | Page 22 of 24
When the CFR1<3> bit is high and the PWRDWNCTL input
pin is high, the AD9859 is put into the full power-down mode.
In this mode, all functions are powered down. This includes the
DAC and PLL, which take a significant amount of time to
power up.
When the PWRDWNCTL input pin is high, the individual
power-down bits (CFR1<7>, <5:4>) are invalid (Don’t Care)
and unused. When the PWRDWNCTL input pin is low, the
individual power-down bits control the power-down modes of
operation.
Note that the power-down signals are all designed such that a
Logic 1 indicates the low power mode and a Logic 0 indicates
the active or power-up mode.
Table 8 indicates the logic level for each power-down bit that
drives out of the AD9859 core logic to the analog section and
the digital clock generation section of the chip for the external
power-down operation.
Layout Considerations
For the best performance, these layout guidelines should be
observed. Always provide the analog power supply (AVDD) and
the digital power supply (DVDD) on separate supplies, even if
just from two different voltage regulators driven by a common
supply. Likewise, the ground connections (AGND, DGND)
should be kept separate as far back to the source as possible (i.e.,
separate the ground planes on a localized board, even if the
grounds connect to a common point in the system). Bypass
capacitors should be placed as close to the device pin as possi-
ble. Usually, a multitiered bypassing scheme consisting of a
small high frequency capacitor (100 pF) placed close to the sup-
ply pin and progressively larger capacitors (0.1 μF, 10 μF) further
away from the actual supply source works best.
Table 8. Power-Down Control Functions
Control
PWRDWNCTL = 0 CFR1<3> Don’t Care
Mode Active
Software Control
Description
Digital Power-Down = CFR1<7>
DAC Power-Down = CFR1<5>
Input Clock Power-Down = CFR1<4>
Digital Power-Down = 1’b1
DAC Power-Down = 1’b0
Input Clock Power-Down = 1’b0
Digital Power-Down = 1’b1
DAC Power-Down = 1’b1
Input Clock Power-Down = 1’b1
PWRDWNCTL = 1 CFR1<3> = 0
External Control,
Fast Recovery Power-Down Mode
PWRDWNCTL = 1 CFR1<3> = 1
External Control,
Full Power-Down Mode
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9859/PCB | 制造商:Analog Devices 功能描述:NCO, 400MSPS 10 BIT, 1.8V CMOS DIRECT DGTL SYNTHESIZER - Bulk |
| AD9859/PCBZ | 功能描述:BOARD EVAL FOR AD9859 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9859/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit,1.8 V CMOS Direct Digital Synthesizer |
| AD9859_09 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9859YSV | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 10-Bit Serial 48-Pin TQFP EP 制造商:Analog Devices 功能描述:DDS 10BIT DAC 400MSPS SMD 9859 |
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