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參數(shù)資料
| 型號： | AD9859 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | 400 MSPS的10位，1.8伏的CMOS直接數(shù)字頻率合成 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 574K |
| 代理商： | AD9859 |
AD9859
AUTO Shaped On-Off Keying Mode Operation
The auto-shaped on-off keying mode is active when CFR1<25>
and CFR1<24> are set. When auto-shaped on-off keying mode
is enabled, a single scale factor is internally generated and
applied to the multiplier input for scaling the output of the DDS
core block (see Figure 18). The scale factor is the output of a
10-bit counter that increments/decrements at a rate determined
by the contents of the 8-bit output ramp rate register. The scale
factor increases if the OSK pin is high and decreases if the OSK
pin is low. The scale factor is an unsigned value such that all 0s
multiply the DDS core output by 0 (decimal) and 0x3FFF mul-
tiplies the DDS core output by 16383 (decimal).
Rev. 0 | Page 17 of 24
For users who use the full amplitude (10-bits) but need fast
ramp rates, the internally generated scale factor step size
is controlled via the ASF<15:14> bits. Table 6 describes the
increment/decrement step size of the internally generated scale
factor per the ASF<15:14> bits.
A special feature of this mode is that the maximum output
amplitude allowed is limited by the contents of the amplitude
scale factor register. This allows the user to ramp to a value less
than full scale.
Table 6. Auto-Scale Factor Internal Step Size
ASF<15:14> (Binary)
Increment/Decrement Size
00
1
01
2
10
4
11
8
OSK Ramp Rate Timer
The OSK ramp rate timer is a loadable down-counter, which
generates the clock signal to the 10-bit counter that generates
the internal scale factor. The ramp rate timer is loaded with the
value of the ASFR every time the counter reaches 1 (decimal).
This load and countdown operation continues for as long as the
timer is enabled, unless the timer is forced to load before reach-
ing a count of 1.
If the load OSK timer bit (CFR1<26>) is set, the ramp rate timer
is loaded upon an I/O UPDATE or upon reaching a value of 1.
The ramp timer can be loaded before reaching a count of 1 by
three methods.
Method one is by changing the OSK input pin. When the OSK
input pin changes state, the ASFR value is loaded into the ramp
rate timer, which then proceeds to count down as normal.
The second method in which the sweep ramp rate timer can be
loaded before reaching a count of 1 is if the load OSK timer bit
(CFR1<26>) is set and an I/O UPDATE is issued.
The last method in which the sweep ramp rate timer can be
loaded before reaching a count of 1 is when going from the
inactive auto-shaped on-off keying mode to the active auto-
shaped on-off keying mode; that is, when the sweep enable bit is
being set.
0
OSK PIN
LOAD OSK TIMER
CFR1<26>
SYNC_CLK
AUTO DESK
ENABLE
CFR1<24>
TO DAC
AUTO SCALE
FACTOR GENERATOR
RAMP RATE TIMER
CLOCK
DDS CORE
OSK ENABLE
CFR<25>
AMPLITUDE SCALE
FACTOR REGISTER
(ASF)
0
0
1
0
1
0
1
HOLD
UP/DN
INC/DEC ENABLE
OUT
COS(X)
AMPLITUDE RAMP
RATE REGISTER
(ASF)
DATA
LOAD
EN
Figure 18. On-Off Shaped Keying, Block Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9859/PCB | 制造商:Analog Devices 功能描述:NCO, 400MSPS 10 BIT, 1.8V CMOS DIRECT DGTL SYNTHESIZER - Bulk |
| AD9859/PCBZ | 功能描述:BOARD EVAL FOR AD9859 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9859/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit,1.8 V CMOS Direct Digital Synthesizer |
| AD9859_09 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9859YSV | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 10-Bit Serial 48-Pin TQFP EP 制造商:Analog Devices 功能描述:DDS 10BIT DAC 400MSPS SMD 9859 |
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