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參數資料
| 型號： | AD9870 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | 1.40 MM HEIGHT, PLASTIC, TQFP-48 |
| 文件頁數： | 15/20頁 |
| 文件大?。?/td> | 233K |
| 代理商： | AD9870 |
REV. 0
AD9870
–15–
Variable Gain Control
When in variable gain mode, the gain of the VGA can be adjusted
by writing to the 16-bit AGCR register. Note, proper loading of
the AGCR register requires that address 0x03 always be writ-
ten prior to 0x04. The maximum update rate of the AGCG
register is f
CLK
/100. The MSB of this register is the bit which
enables 16 dB of attenuation in the preamp. This feature
allows the AD9870 to cope with large level signals beyond
the VGA’s range to prevent overloading of the ADC.
The gain of the VGA is set by an 8-bit control DAC which
provides a differential control signal to the VGA appearing at
pins GCP and GCN. Two external 0.1
μ
F capacitors, C
DAC
,
from GCP and GCN to analog ground, are required to “smooth”
or filter the DAC’s output each time it updates. Note, the dif-
ferential equivalent value of these two capacitors (i.e., C
DAC/2
)
in combination with the DAC’s programmable output resis-
tance sets the –3 dB bandwidth and time constant associated
with this RC network.
Automatic Gain Control (AGC)
The gain of the VGA is automatically adjusted when the AGC is
enabled via the AGCR register. In this mode, the gain of the
VGA is continuously updated in an attempt to ensure that the
maximum signal level into the ADC does not exceed a fixed
analog ADC clip level and that the rms output level of the ADC
is equal to a programmable reference level. This programmable
level can be set at 3 dB, 6 dB, 9 dB, 12 dB, and 15 dB below
the ADC saturation (clip level) by writing values from 1 to 5 to
the 3-bit AGCR field. Note, the ADC clip level is defined to be
–2 dBFS of its full-scale (i.e., 0.28 V rms). If AGCR is 0, auto-
matic gain control is disabled.
The AGC control loop and estimation circuitry are implemented
both in the analog and digital domain to cope with out-of-band
interferers and in-band signals which could otherwise overload
the ADC. If the largest signal into the ADC falls outside the
passband of the first stage digital filter and exceeds the ADC
clip level of –2 dBFS, a control loop based on an analog com-
parator is used to reduce the VGA gain and prevent ADC clipping.
If the largest signal into the ADC is the target signal (and/or
interferer) falling within the passband defined by the first deci-
mation filter (but below the ADC clip level), a control loop
based on a digital estimation of the signal power is used to con-
trol the VGA gain.
Referring to Figure 10, an analog comparator is used to com-
pare the VGA output (or ADC input) to a reference threshold
which is close to that of the ADC clip level. The output of the
comparator will be a digital signal named “OLW” which drives
the digital integrator within the AGC control loop when an over-
load condition is detected. Note, the detection of an overload
condition via this analog signal estimation path takes precedence
over the digital signal estimation path in the AGC control loop
until the analog overload condition is removed. For signals
falling within the passband of the first stage decimate-by-20
digital filter, the rms power of the I and Q signal is estimated
digitally by the following equation:
X
EST
[N]
=
A
BS
(
I[N]
) +
A
BS
(
Q[N]
)
As a result, the VGA and other registers involved in the AGC
algorithm are updated at
f
CLK
/20. The number of overload and
ADC reset occurrences within the final I/Q update rate of the
AD9870 as well as the AGC value (8 MSBs) can be read from
the SSI data upon proper configuration.
(1)
A description of the AGC control algorithm and the user adjust-
able parameters follows. First consider the situation in which the
in-band signal is bigger than all out-of-band signals. In this case,
the amplitude of the in-band signal will be tracked to the pro-
grammed reference level by the AGC using the output of the
digital estimation block. If the difference is negative (i.e., the
signal is too large), the gain is decreased with a proportionality
constant determined by the AGCA setting. Large AGCA values
result in large gain changes thus rapid tracking of changes in
signal strength. If the difference between the target and estimated
signal level is positive (i.e., the signal is too small), the gain is
increased but now the proportionality constant is determined by
both the AGCA and AGCD settings. AGCD is effectively sub-
tracted from AGCA, so large AGCD results in smaller gain
changes and thus slower tracking of fading signals.
The 4-bit code in the AGCA field sets the raw bandwidth of the
AGC loop. With AGCA = 0, the AGC loop bandwidth is at its
minimum of 50 Hz. Each increment of AGCA increases the
loop bandwidth by a factor of 2
1/2
; thus the maximum band-
width is 9 kHz. A general expression for the attack bandwidth is
BW
A
= 50
×
(
f
CLK
/18
MHz
)
×
2
(
AGCA
/2)
Hz
The attack time may be estimated from the loop bandwidth if
one assumes that the loop dynamics are essentially that of a
single-pole system as described by the following equation.
t
ATTACK
= 2.2/(100
×
×
2
AGCA
/2
) = 0.35/
BW
A
This approximation is good if the extra pole caused by the RC
filter on the DAC output is at a sufficiently high frequency. If
the RC pole is placed at four times the raw AGC pole (i.e.,
RC = 1/(8
×
π
×
BW)) then Equation 3 yields an attack time
which is high by about 25%. A more accurate formula for this
case is to replace the 2.2 in the numerator of Equation 3 by 1.7.
The 4-bit code in the AGCD field sets the ratio of the attack
time to the decay time in the amplitude estimation circuitry.
When AGCD is zero, this ratio is one. Incrementing AGCD
multiplies the decay time-constant by 2
1/2
, allowing a 180:1
range in the decay time relative to the attack time. The decay
time may be computed from
t
DECAY
=
t
ATTACK
×
2
(
AGCD
/2)
The 4-bit code in the AGCO field sets the weighting applied
to gain updates when overload is detected. Each increment in
AGCO doubles the weighting factor. At the highest AGCO
setting, each reset event will cause a 6 dB reduction in the
VGA gain.
Lastly, the AGCF bit reduces the DAC source resistance by a
factor of 8. This facilitates fast acquisition by lowering the RC
time constant which is formed with the external capacitors
connected from the GCP and GCN pins to ground. For an
overshoot-free step response in the AGC loop, the capacitors
should be chosen such that the RC time constant is less than
one quarter that of the raw loop. Specifically,
RC
1/(8
π
BW
)
where
R
is the resistance between the GCN and GCP pins and
ground (30 k
±
30% if AGCF = 0, <3.8 k
if AGCF = 1) and
BW
is the raw loop bandwidth. Note that with C chosen at this
upper limit, the loop bandwidth increases by approximately 30%.
(2)
(3)
(4)
(5)
相關PDF資料 |
PDF描述 |
|---|---|
| AD9870EB | IF Digitizing Subsystem |
| AD9873 | Analog Front End Converter for Set-Top Box, Cable Modem |
| AD9873-EB | Analog Front End Converter for Set-Top Box, Cable Modem |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9870AST | 制造商:Rochester Electronics LLC 功能描述:GENERAL PURPOSE IF SUBSYSTEM - Tape and Reel 制造商:Analog Devices 功能描述: |
| AD9870EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem |
| AD9873 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Analog Front End Converter for Set-Top Box, Cable Modem |
| AD9873-EB | 制造商:Analog Devices 功能描述: |
| AD9873JS | 制造商:Analog Devices 功能描述: |
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