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參數(shù)資料
| 型號： | AD9877-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Mixed-Signal Front End Set-Top Box, Cable Modem |
| 中文描述： | 混合信號前端機頂盒，電纜調(diào)制解調(diào)器 |
| 文件頁數(shù)： | 13/36頁 |
| 文件大小： | 1094K |
| 代理商： | AD9877-EB |
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AD9877
THEORY OF OPERATION
To gain a general understanding of the AD9877, refer to the
block diagram of the device architecture in Figure 15. The
following is a general description of the device functionality.
Later sections will detail each of the data path building blocks.
Rev. B | Page 13 of 36
TRANSMIT SECTION
Modulation Mode Operation
The AD9877 accepts 6-bit words that are strobed synchronous
to the master clock, MCLK, into the data assembler. A high
level on TxSYNC signals the start of a transmit symbol. Two
successive 6-bit words form a 12-bit symbol component. The
incoming data is assumed to be complex in that alternating
12-bit words are regarded as the in-phase (I) and quadrature
(Q) components of a symbol. Symbol components are assumed
to be in twos complement format. The rate at which the TxIQ
data is read will be referred to as the master clock rate (f
MCLK
).
The data assembler receives the multiplexed IQ data and creates
two parallel 12-bit paths with I and Q data pairs, which
compose a complex symbol. The rate at which the I and Q data-
word pairs appear at the output of the data assembler are
referred to as the IQ sample rate (f
IQCLK
). Because four 6-bit
reads are required at the TxIQ input to read a full 24-bit
complex symbol, f
MCLK
is 4 times the IQ sample rate (f
MCLK
= 4 ×
f
IQCLK
).
Once through the data assembler, the IQ data streams are fed
through two half-band filters (Half-Band Filters 1 and 2). The
combination of these two filters results in the sample rate
increasing by a factor of 4. Thus, at the output of Half-Band
Filter 2, the sample rate is 4 × f
IQCLK
. In addition to the sample
rate increase, the half-band filters provide the low-pass filtering
characteristic necessary to suppress the spectral images
produced by the upsampling process.
IF12 INPUT
Q INPUT
I INPUT
SDELTA1
XTAL
Tx
FSADJ
SDELTA0
OSCIN
12
8
8
ADC
ADC
ADC
CONTROL WORD 0
CONTROL WORD 1
Σ
-
Δ
Σ
-
Δ
12
12
M = 1, 2, ..., 31
OSCIN
MULTIPLIER
×
M
÷
8
÷
2
÷
2
÷
N
REF12
REF8
÷
2
MUX
DAC
DAC GAIN CONTROL
N = 3, 4
(f
OSCIN
)
(f
OSCIN
)
(f
SYSCLK
)
(f
OSCIN
)
12
QUADRATURE
MODULATOR
DDS
SIN
HALF-BAND
FILTER 1
HALF-BAND
FILTER 2
CIC
FILTER
DATA
ASSEMBLER
I
Q
COS
AD832x CTRL
BURST PROFILE CTRL
SERIAL INTERFACE
3
2
4
RxIQ
DATA
4
12
12
12
12
12
12
12
÷
2
÷
2
R = 2, 3, ..., 63
÷
R
(f
IQCLK
)
(f
MCLK
)
AD9877
6
TxIQ
Rx IF
RxSYNC
RxIQ
REFCLK
MCLK
TxSYNC
0
Figure 15. Block Diagram
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參數(shù)描述 |
|---|---|
| AD9878 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Mixed-Signal Front End for Broadband Applications |
| AD9878BST | 制造商:Analog Devices 功能描述:Mixed Signal Front End 100-Pin LQFP |
| AD9878BSTRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 100-Pin LQFP T/R 制造商:Analog Devices 功能描述:MIXED SGNL FRONT END 100LQFP - Tape and Reel |
| AD9878BSTZ | 功能描述:IC FRONT-END MIXED-SGNL 100-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD9878-EB | 制造商:Analog Devices 功能描述:EVAL KIT FOR MIXED-SGNL FRONT END FOR BROADBAND APPLICATIONS - Bulk |
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