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參數資料
| 型號： | AD9877-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Mixed-Signal Front End Set-Top Box, Cable Modem |
| 中文描述： | 混合信號前端機頂盒，電纜調制解調器 |
| 文件頁數： | 16/36頁 |
| 文件大小： | 1094K |
| 代理商： | AD9877-EB |
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AD9877
RESET AND TRANSMIT POWER-DOWN
Power-Up Sequence
On initial power-up, the RESET pin should be held low until
the power supply is stable.
Rev. B | Page 16 of 36
Once RESET is deasserted, the AD9877 can be programmed
over the serial port. It is recommended that the PWRDN pin be
held low during the reset. Changes to ADC Clock Select
(Register 0x08) or SYS Clock Divider N (Register 0x01) should
be programmed before the rising edge of PWRDN. Changes to
the multiplier (M) will require the PLL to reacquire the new
frequency, which can take up to 1 ms.
Once the PLL is frequency-locked and after the PWRDN pin is
brought high, transmit data can be sent reliably.
If the PWRDN pin cannot be held low throughout the reset and
PLL settling time period, the Power-Down Digital Tx bit or the
PWRDN pin should be pulsed after the PLL has settled. This
will ensure correct transmit filter initialization.
RESET
To initiate a hardware reset, the RESET pin should be held low
for at least 100 ns. All internally generated clocks except
REFCLK stop during reset. The MCLK signal begins
transmission three clock cycles after reset. The rising edge of
RESET reinitializes the programmable registers to their default
values. The same sequence as described in the Power-Up
Sequence section should be followed after a reset or change in M.
A software reset (writing a 1 into Bit 5 of Register 0x00) is
functionally equivalent to the hardware reset but does not force
Register 0x00 to its default value.
0
V
S
1ms
5 MCLK
RESET
PWRDN
Figure 17. Power-Up Sequence for Tx Data Path
Transmit Power-Down
A low level on the PWRDN pin stops all clocks linked to the
digital transmit data path and resets the CIC filter. Deasserting
PWRDN reactivates all clocks. The CIC filter is held in a reset
state for 80 MCLK cycles after the rising edge of PWRDN to
allow for flushing of the half-band filters with new input data.
Transmit data bursts should be padded with at least 20 symbols
of null data directly before the PWRDN pin is asserted.
Immediately after the PWRDN pin is deasserted, the transmit
burst should start with a minimum of 20 null data symbols.
This avoids unintended DAC output samples caused by the
transmit path latency and filter settling time.
Software Power-Down Digital Tx (Bit 5 in Register 0x02) is
functionally equivalent to the hardware PWRDN pin and takes
effect immediately after the last register bit has been written
over the serial port.
PWRDN
TxIQ
TxSYNC
5 MCLK
20 NULL SYMBOLS
DATA SYMBOLS
20 NULL SYMBOLS
0
0
0
0
0
0
0
0
0
Figure 18. Timing Sequence to Flush Tx Data Path
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9878 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Mixed-Signal Front End for Broadband Applications |
| AD9878BST | 制造商:Analog Devices 功能描述:Mixed Signal Front End 100-Pin LQFP |
| AD9878BSTRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 100-Pin LQFP T/R 制造商:Analog Devices 功能描述:MIXED SGNL FRONT END 100LQFP - Tape and Reel |
| AD9878BSTZ | 功能描述:IC FRONT-END MIXED-SGNL 100-LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD9878-EB | 制造商:Analog Devices 功能描述:EVAL KIT FOR MIXED-SGNL FRONT END FOR BROADBAND APPLICATIONS - Bulk |
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