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參數資料
| 型號： | AD9883 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 110 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | 110 MSPS的模擬接口的平板顯示器 |
| 文件頁數： | 11/24頁 |
| 文件大小： | 177K |
| 代理商： | AD9883 |
REV. 0
AD9883
–11–
Timing
The following timing diagrams show the operation of the AD9883.
The Output Data Clock signal is created so that its rising edge
always occurs between data transitions, and can be used to latch
the output data externally.
There is a pipeline in the AD9883, which must be flushed before
valid data becomes available. This means four data sets are
presented before valid data is available.
t
PER
t
CYCLE
t
SKEW
DATACK
DATA
HSOUT
Figure 7. Output Timing
Table V. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Refresh
Rate
Horizontal
Frequency
Standard
Resolution
640
×
480
Pixel Rate
VCORNGE
CURRENT
VGA
60 Hz
72 Hz
75 Hz
85 Hz
31.5 kHz
37.7 kHz
37.5 kHz
43.3 kHz
25.175 MHz
31.500 MHz
31.500 MHz
36.000 MHz
00
00
00
00
101
110
110
110
SVGA
800
×
600
56 Hz
60 Hz
72 Hz
75 Hz
85 Hz
35.1 kHz
37.9 kHz
48.1 kHz
46.9 kHz
53.7 kHz
36.000 MHz
40.000 MHz
50.000 MHz
49.500 MHz
56.250 MHz
00
01
01
01
01
110
100
100
100
101
XGA
1024
×
768
60 Hz
70 Hz
75 Hz
80 Hz
85 Hz
48.4 kHz
56.5 kHz
60.0 kHz
64.0 kHz
68.3 kHz
65.000 MHz
75.000 MHz
78.750 MHz
85.500 MHz
94.500 MHz
01
10
10
10
10
110
100
100
100
100
SXGA
1280
×
1024
60 Hz
64.0 kHz
108.000 MHz
10
110
P0
P1
P2
P3
P4
P5
P6
P7
5-PIPE DELAY
D0
D1
D2
D3
D4
D5
D6
D7
RGB
IN
HSYNC
PxCK
HS
ADCCK
DATACK
D
OUTA
HSOUT
VARIABLE DURATION
Figure 8. Timing Diagram
Hsync Timing
Horizontal Sync (Hsync) is processed in the AD9883 to elimi-
nate ambiguity in the timing of the leading edge with respect to
the phase-delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with respect
to Hsync, through a full 360
°
in 32 steps via the Phase Adjust
register (to optimize the pixel sampling time). Display systems
use Hsync to align memory and display write cycles, so it is
important to have a stable timing relationship between Hsync
output (HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9883. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be pro-
grammed either active high or active low (register 0EH, Bit 5).
Second, HSOUT is aligned with DATACK and data outputs.
Third, the duration of HSOUT (in pixel clocks) is set via regis-
ter 07H. HSOUT is the sync signal that should be used to drive
the rest of the display system.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9883/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS Analog Interface for Flat Panel Displays |
| AD9883A | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883A/PCB | 制造商:Analog Devices 功能描述:110MHZ ANALOG INTERFACE FOR SG |
| AD9883ABST-100 | 制造商:Analog Devices 功能描述:110MHZ ANALOG INTERFACE FOR SGA FPD - Bulk |
| AD9883ABST-110 | 制造商:Analog Devices 功能描述:ADC Triple 110Msps 8-bit Parallel 80-Pin LQFP |
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