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參數(shù)資料
| 型號(hào)： | AD9883 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 110 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | 110 MSPS的模擬接口的平板顯示器 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大小： | 177K |
| 代理商： | AD9883 |
REV. 0
AD9883
–16–
screen, and a slow recovery from large changes in the
Average Picture Level (APL), or brightness.
When Clamp Function = 1, this register is ignored.
Hsync PULSEWIDTH
07
7–0
Hsync Output Pulsewidth
An 8-bit register that sets the duration of the Hsync
output pulse.
The leading edge of the Hsync output is triggered by the
internally generated, phase-adjusted PLL feedback clock.
The AD9883 then counts a number of pixel clocks equal
to the value in this register. This triggers the trailing edge
of the Hsync output, which is also phase-adjusted.
INPUT GAIN
08
7–0
An 8-bit word that sets the gain of the RED channel.
The AD9883 can accommodate input signals with a
full-scale range of between 0.5 V and 1.5 V p-p. Setting
REDGAIN to 255 corresponds to an input range of
1.0 V. A REDGAIN of 0 establishes an input range of
0.5 V. Note that INCREASING REDGAIN results in the
picture having LESS CONTRAST (the input signal
uses fewer of the available converter codes). See Figure 2.
09
7–0
Green Channel Gain Adjust
An 8-bit word that sets the gain of the GREEN channel.
See REDGAIN (08).
0A
7–0
Blue Channel Gain Adjust
An 8-bit word that sets the gain of the BLUE channel.
See REDGAIN (08).
Red Channel Gain Adjust
INPUT OFFSET
0B
7–1
A 7-bit offset binary word that sets the dc offset of the RED
channel. One LSB of offset adjustment equals approximately
one LSB change in the ADC offset. Therefore, the absolute
magnitude of the offset adjustment scales as the gain of the
channel is changed. A nominal setting of 31 results in the
channel nominally clamping the back porch (during the
clamping interval) to Code 00. An offset setting of 63 results
in the channel clamping to Code 31 of the ADC. An offset
setting of 0 clamps to Code –31 (off the bottom of the
range). Increasing the value of Red Offset DECREASES
the brightness of the channel.
0C
7–1
Green Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the
GREEN channel. See REDOFST (0B).
0D
7–1
Blue Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the
GREEN channel. See REDOFST (0B).
Red Channel Offset Adjust
MODE CONTROL 1
0E
7
Hsync Input Polarity Override
This register is used to override the internal circuitry
that determines the polarity of the Hsync signal going
into the PLL.
Table IX. Hsync Input Polarity Override Settings
Override Bit
Function
0
1
Hsync Polarity Determined by Chip
Hsync Polarity Determined by User
The default for Hsync polarity override is 0, (polarity
determined by chip.
6
HSPOL Hsync Input Polarity
A bit that must be set to indicate the polarity of the
Hsync signal that is applied to the PLL Hsync input.
0E
Table X. Hsync Input Polarity Settings
HSPOL
Function
0
1
Active LOW
Active HIGH
Active LOW means the leading edge of the Hsync pulse is
negative-going. All timing is based on the leading edge of
Hsync, which is the FALLING edge. The rising edge has
no effect.
Active high is inverted from the traditional Hsync, with
a positive-going pulse. This means that timing will be
based on the leading edge of Hsync, which is now the
RISING edge.
The device will operate if this bit is set incorrectly, but the
internally generated clamp position, as established by
Clamp Placement (Register 05h), will not be placed as
expected, which may generate clamping errors.
The power-up default value is HSPOL = 1.
5
Hsync Output Polarity
One bit that determines the polarity of the Hsync output
and the SOG output. Table XI shows the effect of this
option. SYNC indicates the logic state of the sync pulse.
0E
Table XI. Hsync Output Polarity Settings
Setting
SYNC
0
1
Logic 1 (Positive Polarity)
Logic 0 (Negative Polarity)
The default setting for this register is 0.
4
Active Hsync Override
This bit is used to override the automatic Hsync selection,
To override, set this bit to Logic 1. When overriding, the
active Hsync is set via Bit 3 in this register.
0E
Table XII. Active Hsync Override Settings
Override
Result
0
1
Auto Determines the Active Interface
Override, Bit 3 Determines the Active Interface
The default for this register is 0.
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| AD9883/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS Analog Interface for Flat Panel Displays |
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| AD9883A/PCB | 制造商:Analog Devices 功能描述:110MHZ ANALOG INTERFACE FOR SG |
| AD9883ABST-100 | 制造商:Analog Devices 功能描述:110MHZ ANALOG INTERFACE FOR SGA FPD - Bulk |
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