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參數(shù)資料
| 型號： | AD9883 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 110 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | 110 MSPS的模擬接口的平板顯示器 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 177K |
| 代理商： | AD9883 |
REV. 0
AD9883
–15–
TWO-WIRE SERIAL CONTROL REGISTER DETAIL
CHIP IDENTIFICATION
00
7–0
Chip Revision
An 8-bit register which represents the silicon revision.
Revision 0 = 0000 0000, Revision 1 = 0000 0001,
Revision 2 = 0000 0010.
PLL DIVIDER CONTROL
01
7–0
PLL Divide Ratio MSBs
The eight most significant bits of the 12-bit PLL divide ratio
PLLDIV. (The operational divide ratio is PLLDIV + 1.)
The PLL derives a master clock from an incoming Hsync
signal. The master clock frequency is then divided by an
integer value, such that the output is phase-locked to
Hsync. This PLLDIV value determines the number of
pixel times (pixels plus horizontal blanking overhead) per
line. This is typically 20% to 30% more than the number
of active pixels in the display.
The 12-bit value of the PLL divider supports divide ratios
from 2 to 4095. The higher the value loaded in this regis-
ter, the higher the resulting clock frequency with respect
to a fixed Hsync frequency.
VESA has established some standard timing specifications,
which will assist in determining the value for PLLDIV as
a function of horizontal and vertical display resolution
and frame rate (Table V).
However, many computer systems do not conform pre-
cisely to the recommendations, and these numbers should
be used only as a guide. The display system manufacturer
should provide automatic or manual means for optimizing
PLLDIV. An incorrectly set PLLDIV will usually produce
one or more vertical noise bars on the display. The greater
the error, the greater the number of bars produced.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69h, PLLDIVL = Dxh).
The AD9883 updates the full divide ratio only when the
LSBs are changed. Writing to the MSB by itself will not
trigger an update.
02
7–4
PLL Divide Ratio LSBs
The four least significant bits of the 12-bit PLL divide ratio
PLLDIV. The operational divide ratio is PLLDIV + 1.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69h, PLLDIVL = Dxh).
The AD9883 updates the full divide ratio only when this
register is written to.
CLOCK GENERATOR CONTROL
03
7–6
VCO Range Select
Two bits that establish the operating range of the clock
generator.
VCORNGE must be set to correspond with the desired
operating frequency (incoming pixel rate).
The PLL gives the best jitter performance at high fre-
quencies. For this reason, in order to output low pixel
rates and still get good jitter performance, the PLL actu-
ally operates at a higher frequency but then divides down
the clock rate afterwards. Table VII shows the pixel rates
for each VCO range setting. The PLL output divisor is
automatically selected with the VCO range setting.
Table VII. VCO Ranges
VCORNGE
Pixel Rate Range
00
01
10
12–36
36–72
72–110
The power-up default value is = 01.
5–3
CURRENT Charge Pump Current
Three bits that establish the current driving the loop filter
in the clock generator.
03
Table VIII. Charge Pump Currents
CURRENT
Current ( A)
000
001
010
011
100
101
110
111
50
100
150
250
350
500
750
1500
CURRENT must be set to correspond with the desired
operating frequency (incoming pixel rate).
The power-up default value is CURRENT = 001.
7–3
Clock Phase Adjust
A five-bit value that adjusts the sampling phase in 32 steps
across one pixel time. Each step represents an 11.25
°
shift
in sampling phase.
The power-up default value is 16.
04
CLAMP TIMING
05
7–0
An eight-bit register that sets the position of the internally
generated clamp.
When Clamp Function (Register 0Fh, Bit 7) = 0, a clamp
signal is generated internally, at a position established by
the clamp placement and for a duration set by the clamp
duration. Clamping is started (Clamp Placement) pixel
periods after the trailing edge of Hsync. The clamp place-
ment may be programmed to any value between 1 and
255. Values of 0, 1, 2, 4, 8, 16, 32, 64, and 128 are not
supported.
The clamp should be placed during a time that the input
signal presents a stable black-level reference, usually the
back porch period between Hsync and the image.
When Clamp Function = 1, this register is ignored.
06
7–0
Clamp Duration
An 8-bit register that sets the duration of the internally
generated clamp.
For the best results, the clamp duration should be set to
include the majority of the black reference signal time that
follows the Hsync signal trailing edge. Insufficient clamp-
ing time can produce brightness changes at the top of the
Clamp Placement
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9883/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS Analog Interface for Flat Panel Displays |
| AD9883A | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883A/PCB | 制造商:Analog Devices 功能描述:110MHZ ANALOG INTERFACE FOR SG |
| AD9883ABST-100 | 制造商:Analog Devices 功能描述:110MHZ ANALOG INTERFACE FOR SGA FPD - Bulk |
| AD9883ABST-110 | 制造商:Analog Devices 功能描述:ADC Triple 110Msps 8-bit Parallel 80-Pin LQFP |
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