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參數(shù)資料
| 型號： | AD9883A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | 110 MSPS/140 MSPS的模擬接口的平板顯示器 |
| 文件頁數(shù)： | 24/28頁 |
| 文件大小： | 229K |
| 代理商： | AD9883A |
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REV. B
AD9883A
–24–
Table XXXVIII. Control of the Sync Block Muxes via the
Serial Register
Serial Bus
Control Bit
Control
Bit State
Mux No.
Result
1 and 2
0EH: Bit 3
0
1
0
1
0
1
Pass Hsync
Pass Sync-on-Green
Pass Coast
Pass Vsync
Pass Vsync
Pass Sync Separator Signal
3
0FH: Bit 5
4
0EH: Bit 0
Sync Slicer
The purpose of the sync slicer is to extract the sync signal from
the Green graphics channel. A sync signal is not present on all
graphics systems, only those with Sync-on-Green. The sync signal
is extracted from the Green channel in a two-step process. First,
the SOG input is clamped to its negative peak (typically 0.3 V
below the black level). Next, the signal goes to a comparator with
a variable trigger level, nominally 0.15 V above the clamped level.
The “sliced” sync is typically a composite sync signal containing
both Hsync and Vsync.
Sync Separator
A sync separator extracts the Vsync signal from a composite sync
signal. It does this through a low-pass filter-like or integrator-like
operation. It works on the idea that the Vsync signal stays active
for a much longer time than the Hsync signal, so it rejects any
signal shorter than a threshold value, which is somewhere between
an Hsync pulsewidth and a Vsync pulsewidth.
The sync separator on the AD9883A is simply an 8-bit digital
counter with a 5 MHz clock. It works independently of the
polarity of the composite sync signal. (Polarities are determined
elsewhere on the chip.) The basic idea is that the counter counts
up when Hsync pulses are present. But since Hsync pulses are
relatively short in width, the counter only reaches a value of N
before the pulse ends. It then starts counting down eventually
reaching 0 before the next Hsync pulse arrives. The specific
value of N will vary for different video modes, but will always be
less than 255. For example with a 1
μ
s width Hsync, the counter
will only reach 5 (1
μ
s/200 ns = 5). Now, when Vsync is present
on the composite sync the counter will also count up. However,
since the Vsync signal is much longer, it will count to a higher
number M. For most video modes, M will be at least 255. So,
Vsync can be detected on the composite sync signal by detecting
when the counter counts to higher than N. The specific count that
triggers detection (T) can be programmed through the serial
register (11H).
Once Vsync has been detected, there is a similar process to detect
when it goes inactive. At detection, the counter first resets to 0,
then starts counting up when Vsync goes away. Similar to the
previous case, it will detect the absence of Vsync when the counter
reaches the threshold count (T). In this way, it will reject noise
and/or serration pulses. Once Vsync is detected to be absent, the
counter resets to 0 and begins the cycle again.
PCB LAYOUT RECOMMENDATIONS
The AD9883A is a high precision, high speed analog device. As
such, to get the maximum performance out of the part, it is
important to have a well laid out board. The following is a guide
for designing a board using the AD9883A.
Analog Interface Inputs
Using the following layout techniques on the graphics inputs is
extremely important.
Minimize the trace length running into the graphics inputs. This
is accomplished by placing the AD9883A as close as possible
to the graphics VGA connector. Long input trace lengths are
undesirable because they pick up more noise from the board
and other external sources.
Place the 75
termination resistors (see Figure 1) as close to the
AD9883A chip as possible. Any additional trace length between
the termination resistors and the input of the AD9883A increases
the magnitude of reflections, which will corrupt the graphics signal.
Use 75
matched impedance traces. Trace impedances other
than 75
will also increase the chance of reflections.
The AD9883A has very high input bandwidth (500 MHz). While
this is desirable for acquiring a high resolution PC graphics
signal with fast edges, it means that it will also capture any high
frequency noise present. Therefore, it is important to reduce the
amount of noise that gets coupled to the inputs. Avoid running
any digital traces near the analog inputs.
Due to the high bandwidth of the AD9883A, low-pass filtering
the analog inputs can sometimes help to reduce noise. (For
many applications, filtering is unnecessary.) Experiments have
shown that placing a series ferrite bead prior to the 75
termi-
nation resistor is helpful in filtering out excess noise. Specifically,
the part used was the #2508051217Z0 from Fair-Rite, but each
application may work best with a different bead value. Alternately,
placing a 100
to 120
resistor between the 75
termination
resistor and the input coupling capacitor can also be beneficial.
Power Supply Bypassing
It is recommended to bypass each power supply pin with a
0.1
μ
F capacitor. The exception is when two or more supply
pins are adjacent to each other. For these groupings of powers/
grounds, it is necessary to have only one bypass capacitor.
The fundamental idea is to have a bypass capacitor within about
0.5 cm of each power pin. Also, avoid placing the capacitor on
the opposite side of the PC board from the AD9883A, as that
interposes resistive vias in the path.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane
to the
capacitor
to the
power pin. Do not make the power
connection between the capacitor and the power pin. Placing a
via underneath the capacitor pads, down to the power plane, is
generally the best approach.
It is particularly important to maintain low noise and good
stability of PV
D
(the clock generator supply). Abrupt changes in
PV
D
can result in similarly abrupt changes in sampling clock phase
and frequency. This can be avoided by careful attention to regu-
lation, filtering, and bypassing. It is highly desirable to provide
separate regulated supplies for each of the analog circuitry
groups (V
D
and PV
D
).
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog supply
regulator, which can in turn produce changes in the regulated
analog supply voltage. This can be mitigated by regulating the
analog supply, or at least PV
D
, from a different, cleaner power
source (for example, from a 12 V supply).
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PDF描述 |
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| AD9883ABST-RL110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883ABST-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883ABST-140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883AKSTZ-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883AKSTZ-140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
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| AD9883A/PCB | 制造商:Analog Devices 功能描述:110MHZ ANALOG INTERFACE FOR SG |
| AD9883ABST-100 | 制造商:Analog Devices 功能描述:110MHZ ANALOG INTERFACE FOR SGA FPD - Bulk |
| AD9883ABST-110 | 制造商:Analog Devices 功能描述:ADC Triple 110Msps 8-bit Parallel 80-Pin LQFP |
| AD9883ABST-140 | 制造商:Analog Devices 功能描述:ADC Triple 140Msps 8-bit Parallel 80-Pin LQFP |
| AD9883ABST-RL110 | 制造商:Analog Devices 功能描述:ADC Triple 110Msps 8-bit Parallel 80-Pin LQFP T/R |
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