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參數資料
| 型號： | AD9954YSV |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理外設 |
| 英文描述： | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | DSP-NUM CONTROLLED OSCILLATOR, PQFP48 |
| 封裝： | EXPOSED PAD, PLASTIC, MS-026-ABC, TQFP-48 |
| 文件頁數： | 13/36頁 |
| 文件大小： | 1027K |
| 代理商： | AD9954YSV |
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AD9954
THEORY OF OPERATION
COMPONENT BLOCKS
DDS Core
The output frequency (
f
O
) of the DDS is a function of the fre-
quency of system clock (SYSCLK), the value of the frequency
tuning word (
FTW
), and the capacity of the accumulator (2
32
, in
this case). The exact relationship is given below with
f
S
defined
as the frequency of SYSCLK.
Rev. 0 | Page 13 of 36
(
)
( )
31
32
2
0
2
≤
≤
=
FTW
with
FTW
(
–
1
f
O
)
(
)
1
–
2
2
2
32
31
32
<
<
×
=
FTW
with
FTW
f
f
S
O
The value at the output of the phase accumulator is translated to
an amplitude value via the COS(x) functional block and routed
to the DAC.
In certain applications it is desirable to force the output signal to
zero phase. Simply setting the FTW to 0 does not accomplish
this; it only results in the DDS core holding its current phase
value. Thus, a control bit is required to force the phase accumu-
lator output to zero.
At power-up, the clear phase accumulator bit is set to Logic 1,
but the buffer memory for this bit is cleared (Logic 0). There-
fore, upon power-up, the phase accumulator will remain clear
until the first I/O UPDATE is issued.
Phase-Locked Loop (PLL)
The PLL allows multiplication of the REFCLK frequency. Con-
trol of the PLL is accomplished by programming the 5-bit
REFCLK multiplier portion of Control Function Register No. 2,
Bits <7:3>.
When programmed for values ranging from 0x04 to 0x14
(4 decimal to 20 decimal), the PLL multiplies the REFCLK input
frequency by the corresponding decimal value. However, the
maximum output frequency of the PLL is restricted to
400 MHz. Whenever the PLL value is changed, the user should
be aware that time must be allocated to allow the PLL to lock
(approximately 1 ms).
The PLL is bypassed by programming a value outside the range
of 4 to 20 (decimal). When bypassed, the PLL is shut down to
conserve power.
Table 5.Clock Input Modes of Operation
CFR1<4>
CLKMODESELECT
Low
High
Low
High
Low
Low
Low
Low
High
X
Clock Input
The AD9954 supports various clock methodologies. Support for
differential or single-ended input clocks, and enabling of an on-
chip oscillator, and/or a phase-locked loop (PLL) multiplier are
all controlled via user programmable bits. The AD9954 may be
configured in one of six operating modes to generate the system
clock. The modes are configured using the CLKMODESELECT
pin, CFR1<4> and CFR2<7:3>. Connecting the external pin
CLKMODESELECT to Logic High enables the on-chip crystal
oscillator circuit. With the on-chip oscillator enabled, users of
the AD9954 connect an external crystal to the REFCLK and
REFCLKB inputs to produce a low frequency reference clock in
the range of 20 MHz to 30 MHz. The signal generated by the
oscillator is buffered before it is delivered to the rest of the chip.
This buffered signal is available via the CRYSTAL OUT pin. Bit
CFR1<4> can be used to enable or disable the buffer, turning on
or off the system clock. The oscillator itself is not powered
down in order to avoid long startup times associated with turn-
ing on a crystal oscillator. Writing CFR2<9> to Logic High
enables the crystal oscillator output buffer. Logic Low at
CFR2<9> disables the oscillator output buffer.
Connecting CLKMODESELECT to Logic Low disables the on-
chip oscillator and the oscillator output buffer. With the oscilla-
tor disabled, an external oscillator must provide the REFCLK
and/or REFCLKB signals. For differential operation, these pins
are driven with complementary signals. For single-ended opera-
tion, a 0.1 μF capacitor should be connected between the
unused pin and the analog power supply. With the capacitor in
place, the clock input pin bias voltage is 1.35 V. In addition, the
PLL may be used to multiply the reference frequency by an
integer value in the range of 4 to 20. Table 5 summarizes the
clock modes of operation. Note the PLL multiplier is controlled
via the CFR2<7:3> bits, independent of the CFR1<4> bit.
CFR2<7:3>
3 < M < 21
M < 4 or M > 20
3 < M < 21
M < 4 or M > 20
X
Oscillator Enabled
Yes
Yes
No
No
No
System Clock
F
CLK
= F
OSC
× M
F
CLK
= F
OSC
F
CLK
= F
OSC
× M
F
CLK
= F
OSC
F
CLK
= 0
Frequency Range (MHz)
80 < F
CLK
< 400
20 < F
CLK
< 30
80 < F
CLK
< 400
10 < F
CLK
< 400
N/A
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相關代理商/技術參數 |
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| AD9954YSV-REEL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9954YSVZ | 功能描述:IC DDS DAC 14BIT 1.8V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9954YSVZ | 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48 |
| AD9954YSVZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9954YSVZ-REEL7 | 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
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