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參數資料
型號: AD9954YSV
廠商: ANALOG DEVICES INC
元件分類: 數字信號處理外設
英文描述: 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer
中文描述: DSP-NUM CONTROLLED OSCILLATOR, PQFP48
封裝: EXPOSED PAD, PLASTIC, MS-026-ABC, TQFP-48
文件頁數: 31/36頁
文件大小: 1027K
代理商: AD9954YSV
AD9954
eight SCLK rising edges. The instruction byte provides the
AD9954 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is read or write and the serial address of the register
being accessed. [Note that the serial address of the register
being accessed is NOT the same address as the bytes to be
written. See the Example Operation section for details].
Rev. 0 | Page 31 of 36
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9954. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9954
and the system controller. The number of bytes transferred
during Phase 2 of the communication cycle is a function of the
.
register being accessed. For example, when accessing the Control
Function Register 2, which is three bytes wide, Phase 2 requires that
three bytes be transferred. If accessing the frequency tuning word,
which is four bytes wide, Phase 2 requires that four bytes be
transferred. After transferring all data bytes per the instruction,
the communication cycle is completed.
At the completion of any communication cycle, the AD9954
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9954 is registered on the rising edge of
SCLK. All data is driven out of the AD9954 on the falling edge
of SCLK. Figure 25 through Figure 28 are useful in understand-
ing the general operation of the AD9954 serial port
0
I
6
I
5
I
4
I
3
I
2
I
1
D
5
D
4
D
3
D
2
D
1
D
0
I
0
D
7
D
6
I
7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
CS
Figure 25. Serial Port Write Timing–Clock Stall Low
0
I
6
I
5
I
4
I
3
I
2
I
1
I
0
DON'T CARE
I
7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
D
O 5
D
O 4
D
O 3
D
O 2
D
O 1
D
O 0
D
O 7
D
O 6
SDO
CS
Figure 26. 3-Wire Serial Port Read Timing–Clock Stall Low
0
I
6
I
5
I
4
I
3
I
2
I
1
D
5
D
4
D
3
D
2
D
1
D
0
I
0
D
7
D
6
I
7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
CS
Figure 27. Serial Port Write Timing–Clock Stall High
0
I
6
I
5
I
4
I
3
I
2
I
1
D
O 5
D
O 4
D
O 3
D
O 2
D
O 1
D
O 0
I
0
D
O 7
D
O 6
I
7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
CS
Figure 28. 2-Wire Serial Port Read Timing—Clock Stall High
相關PDF資料
PDF描述
AD9954YSV-REEL7 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer
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AD9956YCPZ-REEL1 2.7 GHz DDS-Based AgileRF
AD9956YCPZ1 2.7 GHz DDS-Based AgileRF
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相關代理商/技術參數
參數描述
AD9954YSV-REEL7 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9954YSVZ 功能描述:IC DDS DAC 14BIT 1.8V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率(位):10 b 主 fclk:25MHz 調節字寬(位):32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9954YSVZ 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48
AD9954YSVZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer
AD9954YSVZ-REEL7 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率(位):10 b 主 fclk:25MHz 調節字寬(位):32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
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