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參數資料
| 型號： | AD9954YSV |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理外設 |
| 英文描述： | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | DSP-NUM CONTROLLED OSCILLATOR, PQFP48 |
| 封裝： | EXPOSED PAD, PLASTIC, MS-026-ABC, TQFP-48 |
| 文件頁數： | 22/36頁 |
| 文件大小： | 1027K |
| 代理商： | AD9954YSV |
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AD9954
tion bit (CFR1<30>). If CFR1<30> is a Logic 1, the RAM output
is connected to the phase offset adder and supplies the phase
offset control word(s) for the device. When CFR1<30> is Logic
0 (default condition), the RAM output is connected to the input
of the phase accumulator and supplies the frequency tuning
word(s) for the device. When the RAM output drives the phase
accumulator, the phase offset word (POW, Address 0x05) drives
the phase-offset adder. Similarly, when the RAM output drives
the phase offset adder, the frequency tuning word (FTW,
Address 0x04) drives the phase accumulator. When CFR1<31>
is Logic 0, the RAM is inactive unless being written to via the
serial port. The power-up state of the AD9954 is single-tone
mode, in which the RAM enable bit is inactive. The RAM is
segmented into four unique slices controlled by the Profile<1:0>
input pins.
Rev. 0 | Page 22 of 36
All RAM writes/reads, unless otherwise specified, are controlled
by the Profile<1:0> input pins and the respective RAM segment
control word. The RAM can be written to during normal opera-
tion, but any I/O operation that commands the RAM to be writ-
ten immediately suspends read operation from the RAM, causing
the current mode of operation to be nonfunctional. This excludes
single-tone mode, as the RAM is not read in this mode.
Writing the RAM is accomplished as follows. After configuring
the desired RAM segment control words, the desired RAM
segment must be selected via the profile select pins PS<1:0>.
During the instruction byte, write the address for the RAM,
0x0B. The serial port and RAM controller will work in conjunc-
tion to determine the width of the profile and the serial port
will accept the defined number of 32-bit words sequentially
from the beginning address to the ending address. Consider the
following example:
The RAM Segment Control Word 1 lists the beginning
RAM address at 256 and the ending address at 511.
PS0 = 1 and PS1 = 0.
The instruction byte is 10001001.
The RAM controller would configure the serial port to expect
256 32-bit words. The first 32 bits would be parsed as a word
and sent to RAM Address 256. The next 32 bits would be parsed
and sent to 257, and so forth, all the way through until the 256
word was sent (grand total of 8192 data bits in this operation).
MODES OF OPERATION
Single-Tone Mode
In single-tone mode, the DDS core uses a single tuning word.
Whatever value is stored in FTW0 is supplied to the phase
accumulator. This value can only be changed manually, which is
done by writing a new value to FTW0 and by issuing an I/O
UPDATE. Phase adjustment is possible through the phase
offset register.
RAM Controlled Modes of Operation
Direct Switch Mode
Direct switch mode enables FSK or PSK modulation. The
AD9954 is programmed for direct switch mode by writing the
RAM enable bit true and programming the RAM segment
mode control bits of each desired profile to Logic 000(b). This
mode simply reads the RAM contents at the RAM segment
beginning address for the current profile. No address ramping is
enabled in direct switch mode.
To perform 4-tone FSK, the user programs each RAM segment
control word for direct switch mode and a unique beginning
address value. In addition, the RAM enable bit is written true,
which enables the RAM, and the RAM destination bit is written
false, setting the RAM output to be the frequency tuning word.
The Profile<1:0> inputs are the 4-tone FSK data inputs. When
the profile is changed, the frequency tuning word stored in the
new profile is loaded into the phase accumulator and used to
increment the currently stored value in a phase continuous
fashion. The phase offset word drives the phase-offset adder.
Two-tone FSK is accomplished by using only one profile pin for
data.
Programming the AD9954 for PSK modulation is similar to
FSK except the RAM destination bit is set to a Logic 1, enabling
the RAM output to drive the phase offset adder. The FTW0
drives the input to the phase accumulator. Toggling the profile
pins changes (modulates) the current phase value. The upper
14 bits of the RAM drive the phase adder (<31:18>).
Bits <17:0> of the RAM output are unused when the RAM des-
tination bit is set. The no dwell bit is a Don’t Care in direct
switch mode.
Ramp-Up Mode
Ramp-up mode, in conjunction with the segmented RAM capa-
bility, allows up to four different “sweep profiles” to be pro-
grammed into the AD9954. The AD9954 is programmed for
ramp-up mode by writing the RAM enable bit true and pro-
gramming the RAM mode control bits of each profile to be
used to Logic 001(b). As in all modes that enable the memory,
the RAM destination bit controls whether the RAM output
drives the phase accumulator or the phase offset adder.
Upon starting a sweep (via an I/O UPDATE or change in profile
bits), the RAM address generator loads the RAM segment be-
ginning address bits of the current RSCW, driving the RAM
output from this address, and the ramp rate timer loads the
RAM segment address ramp rate bits. When the ramp rate timer
finishes a cycle, the RAM address generator increments to the
next address, the timer reloads the ramp rate bits and begins a
new countdown cycle. This sequence continues until the RAM
address generator has incremented to an address equal to the
RAM segment final address bits of the current RSCW.
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相關代理商/技術參數 |
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| AD9954YSV-REEL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9954YSVZ | 功能描述:IC DDS DAC 14BIT 1.8V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9954YSVZ | 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48 |
| AD9954YSVZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9954YSVZ-REEL7 | 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
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