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參數資料
| 型號： | AD9957BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數： | 31/60頁 |
| 文件大小： | 840K |
| 代理商： | AD9957BSVZ-REEL |
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AD9957
Rev. 0 | Page 31 of 60
START ADDRESS
RAM
ADDRESS
END ADDRESS
1
1 PDCLK CYCLE
OR
M DDS CLOCK CYCLES
Δ
t
I/O_UPDATE OR
RT TRANSITION
2
3
1
Δ
t
0
Figure 45. Continuous Bidirectional Ramp Timing Diagram
RAM Continuous Bidirectional Ramp Mode
In continuous bidirectional ramp mode, upon assertion of an
I/O update or a state change on the RT pin, the RAM begins
playback operation using the parameters programmed into the
selected RAM segment register. Data is extracted from RAM
over the specified address range contained in the start address
and end address. The data is delivered at the appropriate rate
and to the destination as specified by the RAM playback
destination bit.
The playback rate is governed by the timer internal to the RAM
state machine and its period ( t) is determined by the state of
the RAM playback destination bit as detailed in the RAM
P
layback
O
peration section.
After initialization, the internal state machine begins extracting
data from the RAM at the start address of the active RAM
segment register and increments the address counter until it
reaches the end address, at which point the state machine
reverses the direction of the address counter and begins
decrementing through the address range. Whenever one of the
terminal addresses is reached, the state machine reverses the
address counter; the process continues indefinitely.
Note that a change in state of the RT pin aborts the current
waveform and the newly selected RAM segment register is used
to initiate a new waveform.
A graphic representation of the continuous bidirectional ramp
mode is shown in Figure 45. The circled numbers in Figure 45
indicate specific events, explained as follows:
Event 1—an I/O update or state change on the RT pin has
activated the RAM continuous bidirectional ramp mode. The
state machine initializes to the start address of the active RAM
segment register. The state machine begins incrementing
through the specified address range.
Event 2—the state machine reaches the end address of the active
RAM segment register.
Event 3—the state machine reaches the start address of the
active RAM segment register.
This action continues indefinitely until the next I/O update or
state change on the RT pin.
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| AD9958/PCBZ | 功能描述:BOARD EVALUATION FOR AD9958 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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