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參數資料
| 型號： | AD9957BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數： | 50/60頁 |
| 文件大?。?/td> | 840K |
| 代理商： | AD9957BSVZ-REEL |
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AD9957
Control Function Register 1 (CFR1)
Address 0x00, four bytes are assigned to this register.
Rev. 0 | Page 50 of 60
Table 18. Bit Descriptions for CFR1 Register
Bit
No.
Mnemonic
31
RAM Enable
Description
0: disables RAM playback functionality (default).
1: enables RAM playback functionality.
Ineffective unless Bit 31 = 1.
0: RAM playback data routed to baseband scaling multipliers (default).
1: RAM playback data routed to baseband I/Q data path.
00: quadrature modulation mode (default).
01: single tone mode.
1x: interpolating DAC mode.
Ineffective unless Bits<9:8> = 10b.
0: OSK pin inoperative (default).
1: OSK pin enabled for manual OSK control (see the Output Shift Keying (OSK) section).
0: inverse sinc filter bypassed (default).
1: inverse sinc filter active.
This bit is automatically cleared by the serial I/O port controller
.
This operation requires several internal clock
cycles to complete, during which time the data supplied to the CCI input by the baseband signal chain is
ignored. The inputs are forced to all zeros to flush the CCI data path, after which the CCI accumulators are reset.
0: normal operation of the CCI filter (default).
1: initiates an asynchronous reset of the accumulators in the CCI filter.
Ineffective unless Bits<25:24> = 01b.
0: cosine output of the DDS is selected (default).
1: sine output of the DDS is selected.
0: normal operation of the DDS phase accumulator (default).
1: synchronously resets the DDS phase accumulator any time I/O_UPDATE is asserted or a profile
change occurs.
0: normal operation of the DDS phase accumulator (default).
1: asynchronous, static reset of the DDS phase accumulator.
0: normal operation of the OSK amplitude ramp rate timer (default).
1: OSK amplitude ramp rate timer reloaded any time I/O_UPDATE is asserted or a profile change occurs.
0: OSK disabled (default).
1: OSK enabled.
Ineffective unless Bit 9 = 1.
0: manual OSK enabled (default).
1: automatic OSK enabled.
This bit is effective without the need for an I/O update.
0: clock signals to the digital core are active (default).
1: clock signals to the digital core are disabled.
0: DAC clock signals and bias circuits are active (default).
1: DAC clock signals and bias circuits are disabled.
This bit is effective without the need for an I/O update.
0: REFCLK input circuits and PLL are active (default).
1: REFCLK input circuits and PLL are disabled.
0: auxiliary DAC clock signals and bias circuits are active (default).
1: auxiliary DAC clock signals and bias circuits are disabled.
30:20
28
Not Available
RAM Playback
Destination
27:26
25:24
Not Available
Operating Mode
23
Manual OSK
External Control
22
Inverse Sinc Filter
Enable
Clear CCI
21
20:17
16
Not Available
Select DDS Sine
Output
15:14
13
Not Available
Autoclear Phase
Accumulator
12
11
Not Available
Clear Phase
Accumulator
Load ARR @ I/O
Update
OSK (Output Shift
Keying) Enable
Select Auto-OSK
10
9
8
7
Digital Power-
Down
6
DAC Power-Down
5
REFCLK Input
Power-Down
4
Auxiliary DAC
Power-Down
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