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參數資料
| 型號： | AD9958BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | 2-Channel 500 MSPS DDS with 10-Bit DACs |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56 |
| 文件頁數： | 17/40頁 |
| 文件大小： | 1051K |
| 代理商： | AD9958BCPZ |
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AD9958
THEORY OF OPERATION
DDS CORE
The AD9958 has two DDS cores each consisting of a 32-bit
phase accumulator and phase-to-amplitude converter. Together
these digital blocks generate a digital sine wave when the phase
accumulator is clocked and the phase increment value
(frequency tuning word) is greater than 0. The phase-to-
amplitude converter simultaneously translates phase
information to amplitude information by a COS (θ) operation.
Rev. 0 | Page 17 of 40
The output frequency (f
O
) of each DDS channel is a function of
the rollover rate of each phase accumulator. The exact
relationship is given in the following equation:
31
32
2
0
2
)
)(
(
≤
≤
=
FTW
with
f
FTW
f
S
O
where:
f
S
= the system clock rate.
FTW
= the frequency tuning word.
2
32
represents the phase accumulator’s capacity.
Since both channels share a common system clock, they are
inherently synchronized.
The DDS core architecture also supports the capability to phase
offset the output signal. This is performed by the channel phase
offset word (CPOW). The CPOW is a 14-bit register that stores
a phase offset value. This value is added to the output of the
phase accumulator to offset the current phase of the output
signal. Each channel has its own phase offset word register. This
feature can be used for placing both channels in a known phase
relationship relative to one another. The exact value of phase
offset is given by the following equation:
°
×
=
Φ
360
2
14
POW
D/A CONVERTER
The AD9958 incorporates two 10-bit current output DACs. The
DAC converts a digital code (amplitude) into a discrete analog
quantity. The DAC’s current outputs can be modeled as a
current source with high output impedance (typically 100 k).
Unlike many DACs, these current outputs require termination
into AVDD via a resistor or a center-tapped transformer for
expected current flow.
Each DAC has complementary outputs that provide a combined
full-scale output current (I
OUT
+ I
OUTB
). The outputs always sink
current and their sum equals the full-scale current at any point
in time. The full-scale current is controlled by means of an
external resistor (R
SET
) and the scalable DAC current control
bits discussed in the Modes of Operation section. The resistor
R
SET
is connected between the DAC_RSET pin and analog
ground (AGND). The full-scale current is inversely
proportional to the resistor value as follows:
OUT
SET
I
R
91
.
18
=
The maximum full-scale output current of the combined DAC
outputs is 15 mA, but limiting the output to 10 mA provides
optimal spurious-free dynamic range (SFDR) performance. The
DAC output voltage compliance range is AVDD + 0.5 V to
AVDD 0.5 V. Voltages developed beyond this range can cause
excessive harmonic distortion. Proper attention should be paid
to the load termination to keep the output voltage within its
compliance range. Exceeding this range could potentially
damage the DAC output circuitry.
DAC
LPF
IOUT
AVDD
1:1
50
IOUT
0
Figure 31. Typical DAC Output Termination Configuration
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9958BCPZ-REEL7 | 功能描述:IC DDS DUAL 10BIT DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9959 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 Channel 500MSPS DDS with 10-bit DACs |
| AD9959/PCBZ | 功能描述:BOARD EVALUATION FOR AD9959 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9959/PCBZ | 制造商:Analog Devices 功能描述:AD9959, DDS, DAC, GUI, USB, EVALUATION B |
| AD9959/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
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