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參數資料
型號: AD9958BCPZ
廠商: ANALOG DEVICES INC
元件分類: 模擬信號調理
英文描述: 2-Channel 500 MSPS DDS with 10-Bit DACs
中文描述: SPECIALTY ANALOG CIRCUIT, QCC56
封裝: 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56
文件頁數: 26/40頁
文件大?。?/td> 1051K
代理商: AD9958BCPZ
AD9958
OUTPUT AMPLITUDE CONTROL MODE
The 10-bit scale factor (multiplier) controls the ramp-up and
ramp-down (RU/RD) time of an on/off emission from the
DAC. In burst transmissions of digital data, it reduces the
adverse spectral impact of abrupt bursts of data. It can be
bypassed by clearing the multiplier enable bit (ACR <12> = 0).
Rev. 0 | Page 26 of 40
Automatic and manual RU/RD modes are supported. The
automatic mode generates a zero-scale up to a full-scale
(10 bits) linear ramp at a rate determined by the amplitude
ramp rate control register. The start and direction of the ramp
can be controlled by either the profile pins or the SDIO1:3 pins.
Manual mode allows the user to directly control the output
amplitude by manually writing to the amplitude scale factor
value in the amplitude control register (Register 0x06).
Manual mode is enabled by setting the ACR <12> = 1 and
ACR <11> = 0 bits.
Automatic RU/RD Mode Operation
The automatic RU/RD mode is active when both the ACR <12>
and ACR <11> bits are set. When automatic RU/RD is enabled,
the scale factor is internally generated and applied to the multi-
plier input port for scaling the output. The scale factor is the
output of a 10-bit counter that increments/decrements at a
rate set by the 8-bit output ramp rate register. The scale factor
increments if the external pin is high and decrements if the
pin is low. The internally generated scale factor step size is
controlled by the <15:14> bits in the ACR register. Table 21
describes the increment/decrement step size of the internally
generated scale factor per the ACR <15:14> bits.
Table 21.
Autoscale Factor Step Size
ASF <15:14> (Binary)
00
01
10
11
Increment/Decrement
Size
1
2
4
8
A special feature of this mode is that the maximum output
amplitude allowed is limited by the contents of the amplitude
scale factor register (ASFR). This allows the user to ramp to a
value less than full scale.
Ramp Rate Timer
The ramp rate timer is a loadable down counter, which
generates the clock signal to the 10-bit counter that generates
the internal scale factor. The ramp rate timer is loaded with the
value of the ASFR every time the counter reaches 1 (decimal).
This load and count down operation continues for as long as
the timer is enabled unless the timer is forced to load before
reaching a count of 1.
If the load ARR timer bit ACR <10> is set, the ramp rate timer
is loaded at an I/O update, a change in profile input, or on
reaching a value of 1. The ramp timer can be loaded before
reaching a count of 1 by three methods.
1.
In the first method the profile pin(s) or SDIO_1:3 pins are
changed. When the control signal changes state, the ACR
value is loaded into the ramp rate timer, which then
proceeds to count down as normal.
2.
In the second method, the load ARR timer bit (ACR <10>)
is set and an I/O update is issued.
3.
The last method is by changing from inactive auto RU/RD
mode to active auto RU/RD mode.
RU/RD Pin-to-Channel Assignment
1.
When both channels are in single-tone mode, the profile
pins are used for RU/RD operation.
2.
When both linear sweep and RU/RD modes are activated,
SDIO_1:3 are used for RU/RD operation.
3.
In modulation mode, please refer to the modulation mode
section for pin assignments.
Table 22.
Profile Pin
RU/RD Operation
P2
Ch 0
P3
Ch 1
Table 23.
SDIO
LS and RU/RD Modes
Enable
Simultaneously
Enable for CH0
1
1
2
0
3
0
Ramp-Up/Ramp-
Down Control
Signal Assignment
Ramp-up function
for CH0
Ramp-down
function for CH0
Ramp-up function
for CH1
Ramp-down
function for CH1
Enable for CH0
1
0
1
Enable for CH1
1
1
0
Enable for CH1
1
1
1
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