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參數(shù)資料
型號: AD9958BCPZ
廠商: ANALOG DEVICES INC
元件分類: 模擬信號調(diào)理
英文描述: 2-Channel 500 MSPS DDS with 10-Bit DACs
中文描述: SPECIALTY ANALOG CIRCUIT, QCC56
封裝: 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56
文件頁數(shù): 7/40頁
文件大小: 1051K
代理商: AD9958BCPZ
AD9958
Parameter
IAVDD
Both Channels On, Sweep Accumulator,
REF_CLK Multiplier and 10-Bit Output Scalar Enabled
IDVDD
Both Channels On, Single Tone Mode
IDVDD
Both Channels On, Sweep Accumulator,
REF_CLK Multiplier and 10-Bit Output Scalar Enabled
IDVDD_I/O
IDVDD_I/O
IAVDD Power-Down Mode
IDVDD Power-Down Mode
DATA LATENCY (PIPELINE DELAY) SINGLE TONE MODE
2, 3
Frequency, Phase, and Amplitude Words to DAC Output
w/Matched Latency Enabled
Frequency Word to DAC Output w/Matched Latency
Disabled
Phase Offset Word to DAC Output w/Matched Latency
Disabled
Amplitude Word to DAC Output w/Matched Latency
Disabled
DATA LATENCY (PIPELINE DELAY) MODULATION MODE
3
, 4
Frequency Word to DAC Output
Phase Offset Word to DAC Output
Amplitude Word to DAC Output
DATA LATENCY (PIPELINE DELAY) LINEAR SWEEP MODE
3
,
4
Frequency Rising/Falling Delta Tuning Word to DAC
Output
Phase Offset Rising/Falling Delta Tuning Word to DAC
Output
Amplitude Rising/Falling Delta Tuning Word to DAC
Output
1
For the VCO frequency range of 160 MHz to 255 MHz there is no guarantee of operation.
2
Data latency is reference to the I/O_UPDATE>
3
Data latency is fixed.
4
Data latency is referenced to a profile change.
Rev. 0 | Page 7 of 40
Min
Typ
95
Max
110
Unit
mA
Test Conditions/Comments
60
70
70
80
mA
mA
29
22
30
2.5
2.5
mA
mA
mA
mA
Sys Clk
IDVDD = read
IDVDD = write
29
Sys Clk
25
Sys Clk
17
Sys Clk
34
29
21
41
Sys Clk
Sys Clk
Sys Clk
Sys Clk
37
Sys Clk
29
Sys Clk
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參數(shù)描述
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