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參數資料
| 型號： | AD9958BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | 2-Channel 500 MSPS DDS with 10-Bit DACs |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56 |
| 文件頁數： | 34/40頁 |
| 文件大小： | 1051K |
| 代理商： | AD9958BCPZ |
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AD9958
REGISTER MAPS
Rev. 0 | Page 34 of 40
CONTROL REGISTER MAP
Table 27.
Register
Name
(Address)
Range
Channel
Select
Register
(CSR)
(0x00)
Function
Register 1
(FR1)
(0x01)
<15:8>
Bit
Bit 7 (MSB)
Channel 1
enable
1
Bit 6
Channel 0
enable
1
Bit 5
Open
Bit 4
Open
Bit 3
Must be
0
Bit 2
Serial I/0 mode select <2:1>
Bit 1
Bit 0 (LSB)
LSB first
Default
Value
0xF0
<7:0>
<7:0>
Reference clock
input power
down
External power
down mode
Sync clock
disable
DAC reference
power down
Open
Open
Manual
hardware
synchronization
Manual
software
synchronization
0x00
Open
Profile pin configuration <14:12>
Ramp up/ramp
down <11:10>
Modulation Level <9:8>
0x00
<23:16>
VCO gain
control
Multi-device
synchronization
slave enable
PLL divider ratio <22:18>
Charge pump control <17:16>
0x00
Function
Register
Two (FR2)
(0x02)
<7:0>
Multi-device
synchronization
master enable
Multi-device
synchronization
status
Multi-device
synchronization
mask
Open <3:2>
System clock offset <1:0>
0x00
<15:8>
Both channels
auto clear
sweep
accumulator
Both channels
clear sweep
accumulator
Both channels
auto clear
phase
accumulator
Both channels
clear phase
accumulator
Open <11:10>
Open <9:8>
0x00
1
Channel enable bits do not require an I/O update to be activated. These bits are active immediately after the byte containing the bits is written. All other bits need an
I/O update to become active. The two channel enable bits shown in the register map are used to enable/disable any combination of the four channels. Both channels’
default are enabled.
In the CSR register, if the user wants different frequencies for both DDS channels, the following protocol suffices.
1.
Enable (Logic 1) the CH0 bit, which is located in the channel select register and disable the CH1 enable bit (Logic 0).
2.
Write the desired frequency tuning word for CH0, as described in Step 1.
3.
Disable CH0 enable bit (Logic 0) and enable the CH1 bit in the channel select register.
4.
Write the desired frequency tuning word for CH1.
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相關代理商/技術參數 |
參數描述 |
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| AD9958BCPZ-REEL7 | 功能描述:IC DDS DUAL 10BIT DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9959 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 Channel 500MSPS DDS with 10-bit DACs |
| AD9959/PCBZ | 功能描述:BOARD EVALUATION FOR AD9959 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9959/PCBZ | 制造商:Analog Devices 功能描述:AD9959, DDS, DAC, GUI, USB, EVALUATION B |
| AD9959/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
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