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| 型號： | AD9995KCPRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC56 |
| 封裝： | 8 X 8 MM, MO-220-VLLD-2, LFCSP-56 |
| 文件頁數： | 41/60頁 |
| 文件大小： | 1593K |
| 代理商： | AD9995KCPRL |
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AD9995
–41–
Table XIX. Timing Core Register Map
Data Bit Default
Address Content
30
31
Value
0
01001
Register Name
CLIDIVIDE
H1CONTROL
Register Description
Divide CLI Input Clock by 2. 1 = Divide by 2.
H1 Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion).
H1 Positive Edge Location [6:1]. H1 Negative Edge Location [12:7].
H3 Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion).
H3 Positive Edge Location [6:1]. H3 Negative Edge Location [12:7].
RG Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion).
RG Positive Edge Location [6:1]. RG Negative Edge Location [12:7].
Retime HBLK to Internal H1/H3 Clocks. H1 Retime [0]. H3 Retime [1].
Preferred setting is 1 for each bit. Setting each bit to 1 will add one cycle delay
to HBLK toggle positions.
Drive Strength Control for H1 [2:0], H2 [5:3], H3 [8:6], H4 [11:9], and
RG [14:12]. Drive Current Values: 0 = Off, 1 = 4.3 mA, 2 = 8.6 mA,
3 = 12.9 mA, 4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA.
SHP/SHD Sample Control: SHP Sampling Location [5:0].
SHD Sampling Location [11:6].
DOUT Phase Control [5:0]. DCLK Mode [6]. DOUTDELAY [8:7].
[0]
[12:0]
32
[12:0]
01001
H3CONTROL
33
[12:0]
00801
RGCONTROL
34
[1:0]
0
HBLKRETIME
35
[14:0]
1249
DRVCONTROL
36
[11:0]
00024
SAMPCONTROL
37
[8:0]
100
DOUTCONTROL
Table XX. CLPOB Masking Register Map
Data Bit Default
Address Content
40
41
42
Value
FFFFFF CLPMASK01
FFFFFF CLPMASK23
FFFFFF CLPMASK4
Register Name
Register Description
CLPOB Line Masking. Line #0 [11:0]. Line #1 [23:0].
CLPOB Line Masking. Line #2 [11:0]. Line #3 [23:0].
CLPOB Line Masking. Line #4 [11:0].
[23:0]
[23:0]
[11:0]
Table XXI. SG Pattern Register Map
Data Bit Default
Address Content
50
Value
F
Register Name
SGPOL
Register Description
Start Polarity for SG Patterns. Pattern #0 [0]. Pattern #1 [1].
Pattern #2 [2]. Pattern #3 [3].
Pattern #0. Toggle Position 1 [11:0]. Toggle Position 2 [23:12].
Pattern #1. Toggle Position 1 [11:0]. Toggle Position 2 [23:12].
Pattern #2. Toggle Position 1 [11:0]. Toggle Position 2 [23:12].
Pattern #3. Toggle Position 1 [11:0]. Toggle Position 2 [23:12].
[3:0]
51
52
53
54
[23:0]
[23:0]
[23:0]
[23:0]
FFFFFF SGTOG12_0
FFFFFF SGTOG12_1
FFFFFF SGTOG12_2
FFFFFF SGTOG12_3
Table XXII. Shutter Control Register Map
Data Bit Default
Address Content
60
Value
0
Register Name
TRIGGER
Register Description
Trigger for VSUB [0], MSHUT [1], STROBE [2], Exposure [3], and
Readout [4]. Note that to trigger the readout to automatically occur after the
exposure period, both exposure and readout should be triggered together.
Number of Fields to Suppress the SUBCK Pulses after the VSG Line.
Number of Fields to Suppress the SUBCK and VSG Pulses.
Set = 1 to disable the VD/HD outputs during exposure (when >1 field).
Number of SUBCK Pulses to Suppress after VSG Line.
Number of SUBCK Pulses per Field.
SUBCK Pulse Start Polarity.
First SUBCK Pulse. Toggle Position 1 [11:0]. Toggle Position 2 [23:0].
Second SUBCK Pulse. Toggle Position 1 [11:0]. Toggle Position 2 [23:0].
[4:0]
61
62
[2:0]
[11:0]
[12]
[11:0]
[23:12]
[0]
[23:0]
[23:0]
2
0
0
0
0
1
FFFFFF SUBCK1TOG
FFFFFF SUBCK2TOG
READOUT
EXPOSURE
VDHDOFF
SUBCKSUPPRESS
SUBCKNUM
SUBCKPOL
63
64
65
66
REV. 0
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