
Low Phase Noise, Fast Settling PLL
Frequency Synthesizer
ADF4193
FEATURES
New, fast settling, fractional-N PLL architecture
Single PLL replaces ping-pong synthesizers
Frequency hop across GSM band in 5 μs with phase settled
by 20 μs
0.5° rms phase error at 2 GHz RF output
Digitally programmable output phase
RF input range up to 3.5 GHz
3-wire serial interface
On-chip, low noise differential amplifier
Phase noise figure of merit: 216 dBc/Hz
Loop filter design possible using ADI SimPLL
APPLICATIONS
GSM/EDGE base stations
PHS base stations
Instrumentation and test equipment
Rev. B
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2006 Analog Devices, Inc. All rights reserved.
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GENERAL DESCRIPTION
The ADF4193 frequency synthesizer can be used to implement
local oscillators in the upconversion and downconversion
sections of wireless receivers and transmitters. Its architecture
is specifically designed to meet the GSM/EDGE lock time
requirements for base stations. It consists of a low noise, digital
phase frequency detector (PFD), and a precision differential
charge pump. There is also a differential amplifier to convert
the differential charge pump output to a single-ended voltage
for the external voltage-controlled oscillator (VCO).
The Σ-Δ based fractional interpolator, working with the N
divider, allows programmable modulus fractional-N division.
Additionally, the 4-bit reference (R) counter and on-chip
frequency doubler allow selectable reference signal (REFIN)
frequencies at the PFD input. A complete phase-locked loop
(PLL) can be implemented if the synthesizer is used with an
external loop filter and a VCO. The switching architecture
ensures that the PLL settles inside the GSM time slot guard
period, removing the need for a second PLL and associated
isolation switches. This decreases cost, complexity, PCB area,
shielding, and characterization on previous ping-pong GSM
PLL architectures.
FUNCTIONAL BLOCK DIAGRAM
0
N COUNTER
SW1
CP
OUT+
CP
OUT–
SW2
REFERENCE
DATA
LE
24-BIT
DATA
REGISTER
CLK
REF
IN
A
GND
1
A
GND
2
D
GND
1
D
GND
2
D
GND
3
SD
GND
SW
GND
V
DD
DGND
LOCK DETECT
R
DIV
N
DIV
SDV
DD
DV
DD
1
DV
DD
2
DV
DD
3
AV
DD
1
V
P
1
V
P
2
V
P
3
R
SET
OUTPUT
MUX
MUX
OUT
–
+
HIGH Z
PHASE
FREQUENCY
DETECTOR
ADF4193
FRACTIONAL
INTERPOLATOR
MODULUS
REG
FRACTION
REG
INTEGER
REG
RF
IN+
RF
IN–
×2
DOUBLER
4-BIT R
COUNTER
/2
DIVIDER
CHARGE
PUMP
–
+
+
–
DIFFERENTIAL
AMPLIFIER
CMR
AIN–
AIN+
A
OUT
SW3
Figure 1.