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參數(shù)資料
| 型號(hào)： | ADF4193BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Low Phase Noise, Fast Settling PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 3500 MHz, QCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32 |
| 文件頁(yè)數(shù)： | 19/28頁(yè) |
| 文件大小： | 437K |
| 代理商： | ADF4193BCPZ |
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ADF4193
CHARGE PUMP REGISTER (R4)
Rev. B | Page 19 of 28
0
DB23
0
DB22
0
DB21
0
DB20
0
DB19
0
DB18
0
DB17
0
DB16
0
DB15
0
DB14
1
DB13
C9
DB12
C8
DB11
C7
DB10
C6
DB9
C5
DB8
C4
DB7
C3
DB6
C2
DB5
C1
DB4
F2
DB3
F1
DB2
C3 (1)
DB1
C2 (0)
DB0
C1 (0)
9-BIT TIMEOUT COUNTER
RESERVED
CBITS
TIMER
0
0
1
1
F2
0
1
0
1
F1
SW1/SW2
SW3
ICP
NOT USED
TIMER SELECT
C9
0
0
0
0
.
.
.
1
1
1
1
C8
0
0
0
0
.
.
.
1
1
1
1
C7
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
C3
0
0
0
0
.
.
.
1
1
1
1
C2
0
0
1
1
.
.
.
0
0
1
1
C1
0
1
0
1
.
.
.
0
1
0
1
TIMEOUT COUNTER
0
1
2
3
.
.
.
508
509
510
511
xPFD CYCLES
0
4
8
12
.
.
.
2032
2036
2040
2044
DELAY μs
1
0
0.15
0.30
0.46
.
.
.
78.15
78.30
78.46
78.61
1
DELAY WITH 26MHz PFD
Figure 33. Charge Pump Register (R4)
Reserved Bits
Bit DB23 to Bit DB14 are reserved and should be set to hex
code 001 for normal operation.
9-Bit Timeout Counter
These bits are used to program the fast lock timeout counters.
The counters are clocked at one-quarter the PFD reference
frequency, therefore, their time delay scales with the PFD
frequency according to
Delay
(
s
) = (
Timeout Counter Value
× 4)/(
PFD Frequency
)
For example, if 35 were loaded with timer select (00) with a
13 MHz PFD, then SW1/SW2 would be switched after
(35 × 4)/13 MHz = 10.8 μs
Timer Select
These two address bits select the timeout counter to be
programmed. Note that to set up the ADF4193 correctly
requires setup of these three timeout counters; therefore, three
writes to this register are required in the initialization sequence.
Table 6 shows example values for a GSM Tx synthesizer with a
60 kHz final loop BW. See the Applications section for more
information.
Table 6. Recommended Values for a GSM Tx LO
Timer Select
10
01
00
Timeout Counter
ICP
SW1/2
SW3
Value
28
35
35
Time (μs) with
PFD = 13 MHz
8.6
10.8
10.8
On each write to R0, the timeout counters start. Switch SW3
closes until the SW3 counter times out. Similarly, switches
SW1/SW2 close until the SW1/SW2 counter times out. When
the ICP counter times out, the charge pump current is ramped
down from 64× to 1× in six binary steps. It is recommended
that the SW1, SW2, and SW3 timeout counter values are set
equal to the ICP timeout counter value plus 7, as in the example
of Table 6.
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| ADF4193BCPZ-RL | 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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