- 您現在的位置：買賣IC網 > PDF目錄374019 > ADP3166JRU-REEL (ANALOG DEVICES INC) 5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller PDF資料下載
參數資料
| 型號： | ADP3166JRU-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller |
| 中文描述： | SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | TSSOP-28 |
| 文件頁數： | 15/20頁 |
| 文件大小： | 351K |
| 代理商： | ADP3166JRU-REEL |
REV. 0
ADP3166
–15–
Ramp Resistor Selection
The ramp resistor (R
R
) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. The following expression is used for determining the
optimum value:
R =
A
L
A
0 2
5
R
600nH
4. mW
C
R =
.
pF=
k
R
×
×
D
DS
R
×
×
×
×
×
×
3
3
5
381
(19)
where
A
R
is the internal ramp amplifier gain,
A
D
is the current
balancing amplifier gain,
R
DS
is the total low-side MOSFET on
resistance, and
C
R
is the internal ramp capacitor value. The
closest standard 1% resistor value is 383 k
.
The internal ramp voltage magnitude can be calculated using
V =A
– D
C
– .
×
5
V
R
.
f
V =
kHz=0 41
330
k
pF
V
R
VID
R
R
SW
×
(
)
×
×
×
×
(
)
×
×
1
0 2
383
1 0 125
1. V
(20)
The size of the internal ramp can be made larger or smaller. If it
is made larger, stability and transient response will improve, but
thermal balance will degrade. Conversely, if the ramp is made
smaller, thermal balance will improve at the sacrifice of transient
response and stability. The factor of three in the denominator of
Equation 19 sets a ramp size that gives an optimal balance for
good stability, transient response, and thermal balance.
COMP Pin Ramp
There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds to
the internal ramp to produce the following overall ramp signal
at the PWM input.
V
=
V
–
R + R
f
SW
×
– nD
×
n
C
R
R
RT
R
OD
X
O
OD
1
1
(
)
×
(
×
)
×
(21)
For this example, the overall ramp signal is found to be 0.48 V.
Current Limit Set Point
To select the current limit set point, we need to find the resistor
value for
R
LIM
. The current limit threshold for the ADP3166 is
set with a 3 V source (
V
LIM
) across
R
LIM
with a gain of 10.4 mV/
μ
A
(
A
LIM
).
R
LIM
can be found using the following:
R
=A
V
×
I
R
LIM
LIM
LIM
LIM
O
×
(22)
For values of
R
LIM
greater than 500 k
, the current limit may be
lower than expected, so some adjustment of
R
LIM
may be needed.
Here,
I
LIM
is the average current limit for the output of the sup-
ply. For our example, choosing 75 A for
I
LIM
, we find
R
LIM
to be
378 k
, for which we choose 374 k
as the nearest 1% value.
The per phase current limit described earlier has its limit deter-
mined by the following:
I
V
–V –V
R
DS(MAX)
A
–I
PHLIM
COMP(MAX)
BIAS
D
R
×
2
(23)
For the ADP3166, the maximum COMP voltage
(V
COMP(MAX))
is 3.3 V, the COMP pin bias voltage (
V
BIAS
) is 1.2 V, and the
current balancing amplifier gain (
A
D
) is 5. Using V
R
of 0.48 V,
and R
DS(MAX)
of 4.2 m
(low-side on resistance at 150
°
C), we
find a per phase limit of 74 A.
This limit can be adjusted by changing the ramp voltage V
R
. But
make sure not to set the per phase limit lower than the average
per phase current (I
LIM/n
).
There is also a per phase initial duty cycle limit determined by:
D
= D
V
–V
V
MAX
COMP MAX
BIAS
RT
×
)
(24)
For this example, the maximum duty cycle is found to be 0.55.
Feedback Loop Compensation Design
Optimized compensation of the ADP3166 allows the best pos-
sible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make the
regulator and output decoupling appear as an output impedance
that is optimized over the widest possible frequency range,
including dc, and equal to the droop resistances (R
O
and
R
OD
). With the output impedance, the output voltage will respond
in proportion with the load current; this ensures the optimal
output positioning and allows the minimization of the output
decoupling.
With the multimode feedback structure of the ADP3166, one
needs to set the feedback compensation to make the converter’s
output impedance work in parallel with the output decoupling to
meet this goal. There are several poles and zeros created by the
output inductor and decoupling capacitors (output filter) that
need to be compensated for.
相關PDF資料 |
PDF描述 |
|---|---|
| ADP3166JRU-REEL7 | 5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller |
| ADP3170JRU | VRM 8.5 Compatible Single Phase Core Controller |
| ADP3170 | Charger front end protection IC with 30V max Vin and 4.5V LDO output 8-WSON 0 to 125 |
| ADP3171JR | Charger front end protection IC with 30V max Vin and 4.5V LDO output 8-WSON 0 to 125 |
| ADP3171 | Charger front end protection IC with 30V max Vin and 4.5V LDO output 8-WSON 0 to 125 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADP3166JRU-REEL7 | 功能描述:IC REG BUCK 5BIT 2-4PHAS 28TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩壓器 - 專用型 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數:10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應商設備封裝:42-WLP 包裝:帶卷 (TR) |
| ADP3166JRUZ-REEL | 功能描述:IC REG BUCK 5BIT 2-4PHAS 28TSSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩壓器 - 專用型 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數:10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應商設備封裝:42-WLP 包裝:帶卷 (TR) |
| ADP3167 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ADP3160/ADP3167: 5-Bit Programmable 2-Phase Synchronous Buck Controller Data Sheet (Rev. B. 5/02) |
| ADP3167JR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADP3167JR-REEL7 | 制造商:Rochester Electronics LLC 功能描述:5BIT PROG'BLE 2 PHASE SYNCRO BUCK CNTRLR - Tape and Reel |
發布緊急采購，3分鐘左右您將得到回復。