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參數資料
| 型號： | ADSP-2163BP-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | RECTIFIER FAST-RECOVERY SINGLE 1.5A 100V 50A-ifsm 1V-vf 50ns 5uA-ir DO-15 1K/BULK |
| 中文描述： | 24-BIT, 25 MHz, OTHER DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數： | 12/39頁 |
| 文件大?。?/td> | 243K |
| 代理商： | ADSP-2163BP-100 |
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REV. 0
ADSP-216x
–12–
Program Flow Instructions
DO <addr> [UNTIL term] ;
[IF cond] JUMP (Ix) ;
[IF cond] JUMP <addr>;
[IF cond] CALL (Ix) ;
[IF cond] CALL <addr>;
IF [NOT ] FLAG_IN
IF [NOT ] FLAG_IN
[IF cond] SET|RESET|TOGGLE
[IF cond] RTS ;
[IF cond] RTI ;
IDLE [(n)] ;
Miscellaneous Instructions
NOP ;
MODIFY (Ix , My);
[PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ;
ENA|DIS
SEC_REG [, ...] ;
BIT_REV
AV_LATCH
AR_SAT
M_MODE
TIMER
G_MODE
Notation Conventions
Ix
Index registers for indirect addressing
My
Modify registers for indirect addressing
<data>
Immediate data value
<addr>
Immediate address value
<exp>
Exponent (shift value) in shift immediate instructions (8-bit signed number)
<ALU>
Any ALU instruction (except divide)
<MAC>
Any multiply-accumulate instruction
<SHIFT>
Any shift instruction (except shift immediate)
cond
Condition code for conditional instruction
term
Termination code for DO UNTIL loop
dreg
Data register (of ALU, MAC, or Shifter)
reg
Any register (including dregs)
;
A semicolon terminates the instruction
,
Commas separate multiple operations of a single instruction
[ ]
Optional part of instruction
[, ...]
Optional, multiple operations of an instruction
option1
|
option2
List of options; choose one.
Assembly Code Example
The following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared
algorithm. Notice that the computations in the instructions are written like algebraic equations.
Do Until Loop
Jump
Call Subroutine
JUMP <addr>;
CALL <addr>;
Jump/Call on Flag In Pin
FLAG_OUT [, ...] ;
Modify Flag Out Pin
Return from Subroutine
Return from Interrupt Service Routine
Idle
No Operation
Modify Address Register
Stack Control
Mode Control
MF=MX0*MY1(RND), MX0=DM(I2,M1);
MR=MX0*MF(RND), AY0=PM(I6,M5);
DO adapt UNTIL CE;
AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7);
PM(I6,M6)=AR, MR=MX0*MF(RND);
{MF=error*beta}
adapt:
MODIFY(I2,M3);
MODIFY(I6,M7);
{Point to oldest data}
{Point to start of data}
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-2163BP-66 | DSP Microcomputers with ROM |
| ADSP-2163BS-100 | 100V 1A ULTRA FAST LOW-LOSS CONTROLLED AVALANCHE RECTIFIER, SMA US1 SERIES, DO- |
| ADSP-2163BS-66 | DSP Microcomputers with ROM |
| ADSP-2163KS-100 | DSP Microcomputers with ROM |
| ADSP-2163KS-66 | DSP Microcomputers with ROM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-2163BP-1002 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163BP-66 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163BP-662 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163BS-100 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163BS-1002 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
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