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參數資料
| 型號： | ADSP-2163BP-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | RECTIFIER FAST-RECOVERY SINGLE 1.5A 100V 50A-ifsm 1V-vf 50ns 5uA-ir DO-15 1K/BULK |
| 中文描述： | 24-BIT, 25 MHz, OTHER DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數： | 4/39頁 |
| 文件大?。?/td> | 243K |
| 代理商： | ADSP-2163BP-100 |
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ADSP-216x
–4–
Efficient data transfer is achieved with the use of five internal
buses:
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
The two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
The
BMS
,
DMS
and
PMS
signals indicate which memory space
is using the external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-216x to fetch two operands in a single cycle,
one from program memory and one from data memory. The
processor can fetch an operand from on-chip program memory
and the next instruction in the same cycle.
The memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (
BR
,
BG
).
One bus grant execution mode (GO Mode) allows the ADSP-
216x to continue running from internal memory. A second
execution mode requires the processor to halt while buses are
granted.
Each ADSP-216x processor can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer and serial ports. There is also a master
RESET
signal.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. This allows, for
example, a 60 ns ADSP-2161 to use a 200 ns EPROM as
external boot memory. Multiple programs can be selected and
loaded from the EPROM with no additional hardware.
The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every
n
cycles, where
n–1
is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-216x processors include two synchronous serial
ports (SPORTs) for serial communications and multiprocessor
communication. All of the ADSP-216x processors have two
serial ports (SPORT0, SPORT1).
The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of opera-
tion are available. Each SPORT can generate an internal pro-
grammable serial clock or accept an external serial clock.
Each serial port has a 5-pin interface consisting of the following
signals:
Signal Name
Function
SCLK
RFS
TFS
DR
DT
Serial Clock (I/O)
Receive Frame Synchronization (I/O)
Transmit Frame Synchronization (I/O)
Serial Data Receive
Serial Data Transmit
OUTPUT REGS
INPUT REGS
OUTPUT REGS
INPUT REGS
OUTPUT REGS
INPUT REGS
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
INSTRUCTION
REGISTER
PROGRAM
SEQUENCER
PROGRAM
MEMORY
SRAM
& ROM
BOOT
ADDRESS
GENERATOR
TIMER
PMA BUS
DMA BUS
PMD BUS
DMD BUS
24
16
BUS
EXCHANGE
COMPANDING
CIRCUITRY
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 1
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
5
5
16
R BUS
ALU
MAC
SHIFTER
PMA BUS
14
14 PMA BUS
DATA
MEMORY
SRAM
EXTERNAL
EXTERNAL
MUX
MUX
24
14
24 PMA BUS
16 PMA BUS
16
Figure 1. ADSP-216x Block Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-2163BP-66 | DSP Microcomputers with ROM |
| ADSP-2163BS-100 | 100V 1A ULTRA FAST LOW-LOSS CONTROLLED AVALANCHE RECTIFIER, SMA US1 SERIES, DO- |
| ADSP-2163BS-66 | DSP Microcomputers with ROM |
| ADSP-2163KS-100 | DSP Microcomputers with ROM |
| ADSP-2163KS-66 | DSP Microcomputers with ROM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-2163BP-1002 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163BP-66 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163BP-662 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163BS-100 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163BS-1002 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
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